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Phase-Aligned Clock Multiplier
CY2300
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07252 Rev. *B
Revised July 26, 2004
Features
• 4-multiplier configuration
• Single phase-locked loop architecture
• Phase Alignment
• Low jitter, high accuracy outputs
• Output enable pin
• 3.3V operation
• 5V Tolerant input
• Internal loop filter
• 8-pin 150-mil SOIC package
• Commercial and Industrial Temperature available
Benefits
• 1/2x, 1x, 1x, 2x Ref
• 10 MHz to 166.67 MHz operating range (reference input
from 20 MHz to 83.33 MHz)
• All outputs will have a consistent phase relationship
with each other and the reference input
• Meets critical timing requirements
• Enables design flexibility and lower power
consumption
• Supports industry standard design platforms
• Allows flexibility on Reference input
• Alleviates the need for external components
• Industry standard packaging saves on board space
• Suitable for wide spectrum of applications
Selector Guide
Part Number
Outputs
Input Frequency Range
Output Frequency Range
Specifics
CY2300SC
4
20 MHz–83.33 MHz
10 MHz–166.67 MHz
Commercial Temperature
CY2300SI
4
20 MHz–83.33 MHz
10 MHz–166.6 7MHz
Industrial Temperature
PLL
1/2xREF
2xREF
REFIN
1
2
3
4
5
8
7
6
1/2xREF
GND
REFIN
REF
VDD
OE
REF
Top View
8-pin SOIC
2xREF
REF
Block Diagram
Pin Configuration
Divider
Logic
FBK
/2
OE
REF
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