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MC100EP16VCDTR2 Datasheet(PDF) 2 Page - ON Semiconductor

Part # MC100EP16VCDTR2
Description  3.3V / 5V ECL Differential Receiver/Driver with High Gain and Enable Output
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC100EP16VCDTR2 Datasheet(HTML) 2 Page - ON Semiconductor

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MC100EP16VC
http://onsemi.com
2
Figure 1. 8−Lead Pinout (Top View) and Logic Diagram
PIN
FUNCTION
PIN DESCRIPTION
D*
ECL Data Input
Q
ECL Data Output
QHG, QHG
ECL High Gain Data Outputs
EN*
ECL Enable Input
VBB/D
Reference Voltage Output / ECL Data Input
VCC
Positive Supply
VEE
Negative Supply
1
2
3
45
6
7
8
QHG
VEE
VCC
D
QHG
EN
VBB/D
Q
VBB
D
LEN
Q
LATCH
OE
* Pins will default LOW when left open.
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
W
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
167 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
−6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VI v VCC
VI w VEE
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 1.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
std bd
8 SOIC
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
std bd
8 TSSOP
41 to 44
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248
°C
265
°C
2. Maximum Ratings are those values beyond which device damage may occur.


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