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M5M51R16AWG-10LI Datasheet(PDF) 4 Page - Mitsubishi Electric Semiconductor |
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M5M51R16AWG-10LI Datasheet(HTML) 4 Page - Mitsubishi Electric Semiconductor |
4 / 7 page MITSUBISHI LSIs 1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM M5M51R16AWG -10LI, -12LI, -15LI, -10HI, -12HI, -15HI MITSUBISHI ELECTRIC Aug.1. 1998 4 AC ELECTRICAL CHARACTERISTICS ( Ta = - 40 ~85°C, Vcc = 1.8V~2.7V, unless otherwise noted ) (1) MEASUREMENT CONDITIONS Input pulse level • • • • • • • VIH = 0.7 x Vcc + 0.2V, VIL = 0.2V Input rise and fall time • • • • 5ns Reference level • • • • • • • • VOH = 0.9V, VOL = 0.9V Transition is measured ±200mV from steady state voltage. ( for ten, tdis ) Output loads • • • • • • • • • Fig.1,CL = 30pF CL = 5pF ( for ten, tdis ) DQ Fig.1 Output load CL ( Including scope and JIG ) 1 TTL (3)WRITE CYCLE Symbol Parameter Write cycle time Address set up time Address set up time with respect to W Write pulse width Data set up time Data hold time BC1 setup time Chip select set up time BC2 setup time Write recovery time Output enable time after W high Output enable time after OE low Output disable time after W low Output disable time after OE high tCW tw(W) tsu(A) tsu(A-WH) tsu(BC1) tsu(BC2) tsu(S) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) 120 0 100 85 55 0 100 100 5 100 0 40 5 40 10 10 Output enable time after BC1 low ten(BC1) Output enable time after BC2 low ten(BC2) Unit -15LI,-15HI Max Min ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Limits -12LI,-12HI Max Min -10LI,-10HI Max Min 0 75 50 0 85 5 85 0 35 5 35 10 10 0 100 60 0 120 5 120 0 50 5 50 10 10 100 85 85 150 120 120 ns (2)READ CYCLE Symbol Parameter Unit -15LI,-15HI Max Min Output enable access time ns 75 Output disable time after S high ns 50 Read cycle time ns 150 Address access time ns 150 ns BC1 access time 150 ns Chip select access time 150 Output enable time after S low ns 10 Data valid time after address change ns 10 BC2 access time ns 150 Output disable time after BC1 high ns 50 Output disable time after BC2 high ns 50 Output disable time after OE high ns 50 Output enable time after BC1 low ns 10 Output enable time after BC2 low ns 10 Output enable time after OE low ns 5 tCR ta(A) ta(BC1) ta(BC2) ta(S) ta(OE) tdis(BC1) tdis(BC2) tdis(S) tdis(OE) ten(BC1) ten(BC2) ten(S) ten(OE) tV(A) Limits -12LI,-12HI Max Min 60 40 120 120 120 120 10 10 120 40 40 40 10 10 5 -10LI,-10HI Max Min 50 35 100 100 100 100 10 10 100 35 35 35 10 10 5 |
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