© Semiconductor Components Industries, LLC, 1999

September, 1999 – Rev. 1.0

1

Publication Order Number:

MC100EPT21/D

MC100EPT21

Differential LVPECL to

LVTTL Translator

The MC100EPT21 is a Differential LVPECL to LVTTL translator.

Because LVPECL (Positive ECL) levels are used only +3.3V and

ground are required. The small outline 8–lead SOIC package makes

the EPT21 ideal for applications which require the translation of a

clock or data signal.

The VBB output allows the EPT21 to also be used in a single–ended

input mode. In this mode the VBB output is tied to the D0 input for a

non–inverting buffer or the D0 input for an inverting buffer. If used,

the VBB pin should be bypassed to ground via a 0.01

µF capacitator.

For Additional Information, See Application Note AND8003/D

Oxygen Index 28 to 34

1

2

3

45

6

7

8

Q

GND

VCC

Figure 1. 8–Lead Pinout (Top View) and Logic Diagram

D

NC

D

VBB

NC

LVTTL

LVPECL

ALYW

SO–8

D SUFFIX

CASE 751

PIN DESCRIPTION

PIN

Q

D, D

Differential LVPECL Input Pair

FUNCTION

LVTTL Output

http://onsemi.com

VCC

VBB

Output Reference Voltage

Positive Supply

GND

Ground

MARKING DIAGRAM

Device

Package

Shipping

ORDERING INFORMATION

MC100EPT21D

SOIC

98 Units/Rail

MC100EPT21DR2

SOIC

2500 Tape & Reel

KPT21

1

8

1

8

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

*For additional information, see Application Note

AND8002/D