5

INDUSTRIALTEMPERATURERANGE

IDT5T2110

2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK

PIN DESCRIPTION, CONTINUED

Symbol

I/O

Type

Description

REF_SEL

I

nsOE

I

Synchronousoutputenable. WhennsOE isHIGH,nQandnQ aresynchronouslystopped. OMODEselectswhethertheoutputsare

gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/HIGH,

the nQ is stopped in a HIGH/LOW state, while the nQ is stopped at a LOW/HIGH state. When OMODE is LOW, the outputs are tri-

stated. Set nsOE LOW for normal operation.

QFB

O

Feedbackclockoutput

QFB

O

Complementaryfeedbackclockoutput

nQ

O

Clockoutputs

nQ

O

Complementaryclockoutputs

RxS

I

Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) REF clock input or differential (LOW) REF clock input

TxS

I

Setsthedrivestrengthoftheoutputdriversandfeedbackinputstobe2.5VLVTTL(HIGH),1.8VLVTTL(MID)oreHSTL/HSTL(LOW)

PE

I

Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedgeofthereference

clock(hasinternalpull-up).

I

Function select inputs for divide-by-2, divide-by-4, zero delay, or invert on each bank. (See Control Summary table.)

I

Function select inputs for divide-by-2, divide-by-4, zero delay, or invert on the feedback bank (See Control Summary table)

FS

I

Selectsappropriateoscillatorcircuitbasedonanticipatedfrequencyrange(SeeVCOFrequencyRangeSelecttable)

I

3-levelinputsforfeedbackinputdividerselection(SeeDivideSelectiontable)

PLL_EN

I

PD

I

Powerdowncontrol. WhenPDisLOW,theinputsaredisabledandinternalswitchingisstopped. OMODEselectswhethertheoutputs

are gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/

HIGH, the nQ and QFB are stopped in a HIGH/LOW state, while the nQ and QFB are stopped in a LOW/HIGH state. When OMODE

is LOW, the outputs are tri-stated. Set PD HIGH for normal operation.

LOCK

O

LVTTL

PLLlockindicationsignal. HIGHindicateslock. LOWindicatesthatthePLLisnotlockedandoutputsmaynotbesynchronized tothe

inputs. The output will be 2.5V LVTTL.

OMODE

I

Outputdisablecontrol. Determinestheoutputs'disablestate. UsedinconjunctionwithnsOEandPD. (SeeOutputEnable/Disableand

Powerdowntables.)

PWR

PWR

Powersupplyforphaselockedloop,lockoutput,inputs,andotherinternalcircuitry

GND

PWR

Ground

VCO FREQUENCY RANGE SELECT

Min.

Max.

Unit

LOW

50

125

MHz

HIGH

100

250

MHz

NOTE:

1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the nQ

is stopped in a HIGH/LOW state while the nQ is stopped at a LOW/HIGH state.

OUTPUTENABLE/DISABLE

nsOE

OMODE

Output

L

X

NormalOperation

H

L

Tri-State

H

H

NOTE:

1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the nQ

and QFB are stopped in a HIGH/LOW state, while the nQ and QFB are stopped in a

LOW/HIGH state.

POWERDOWN

PD

OMODE

Output

H

X

NormalOperation

L

L

Tri-State

L

H

NOTE:

1. The level to be set on FS is determined by the nominal operating frequency of the

Divide Selection table).

NOTES:

1. Pins listed as LVTTL inputs will accept 2.5V signals under all conditions. If the output is operating at 1.8V or 1.5V, the LVTTL inputs will accept 1.8V LVTTL signals as well.