AutoShutdown Mode

The ADC automatically powers down on the SCLK

falling edge that clocks out the LSB. This is the falling

edge after the 13th SCLK. DOUT goes low when the

LSB has been clocked into the master (µC) on the 16th

rising SCLK edge.

Alternatively, drive OE high to force the MAX1392/

MAX1395 into power-down. Whenever OE goes high,

the ADC powers down and disables DOUT regardless

of CS, SCLK, or the state of the ADC. DOUT enters a

External Reference

The MAX1392/MAX1395 use an external reference

0.1µF capacitor to GND for best performance (see the

Typical Operating Circuit).

Serial Interface

The MAX1392/MAX1395 serial interface is fully compati-

ble with SPI, QSPI, and MICROWIRE (see Figure 7). If a

serial interface is available, set the µC’s serial interface

in master mode so the µC generates the serial clock.

Choose a clock frequency between 100kHz and 5MHz.

CS and OE can be connected together and driven

simultaneously. OE can also be connected to GND if the

DOUT bus is not shared and driven independently.

SPI and MICROWIRE

When using SPI or MICROWIRE, make the µC the bus

master and set CPOL = 0 and CPHA = 0 or CPOL = 1

and CPHA = 1. (These are the bits in the SPI or

MICROWIRE control register.) Two consecutive 1-byte

reads are required to get the entire 10-bit result from

the ADC. The MAX1392/MAX1395 shut down after

clocking the LSB and DOUT becomes high impedance.

DOUT transitions on SCLK’s falling edge and is

clocked into the µC on the SCLK’s rising edge. See

Figure 7 for connections and Figures 8 and 9 for timing

diagrams. The conversion result contains 4 zeros, fol-

lowed by the 10 data bits with the data in MSB-first for-

mat. When using CPOL = 0 and CPHA = 0 or CPOL = 1

and CPHA = 1, the MSB of the data is clocked into the

µC on the SCLK’s fifth rising edge. To be compatible

with SPI and MICROWIRE, connect CS and OE togeth-

er and drive simultaneously.

QSPI

Unlike SPI, which requires two 1-byte reads to acquire

the 10 bits of data from the ADC, QSPI allows the mini-

mum number of clock cycles necessary to clock in the

data. The MAX1392/MAX1395 require a minimum of 14

clock cycles from the µC to clock out the 10 bits of

data. See Figure 7 for connections and Figures 8 and 9

for timing diagrams. The conversion result contains 4

zeros, followed by the 10 data bits with the data in

MSB-first format. The MAX1392/MAX1395 shut down

after clocking out the LSB. DOUT then becomes high

impedance. When using CPOL = 0 and CPHA = 0 or

CPOL = 1 and CPHA = 1, the MSB of the data is

clocked into the µC on the SCLK’s fifth rising edge. To

be compatible with QSPI, connect CS and OE together

and drive simultaneously.

DSP Interface

Figure 10 shows the timing for DSP operation. Figure 11

shows the connections between the MAX1392/

MAX1395 and several common DSPs.

______________________________________________________________________________________

11

1.5V to 3.6V, 357ksps, 1-Channel True-Differential/

2-Channel Single-Ended, 10-Bit, SAR ADCs

MAX1392

MAX1395

OE

a) SPI

I/O

SCK

CS

DOUT

MISO

I/O

UNI/BIP

(CH1/CH2)*

SCLK

MAX1392

MAX1395

OE

CS

SCK

CS

DOUT

MISO

I/O

UNI/BIP

(CH1/CH2)*

SCLK

MAX1392

MAX1395

OE

I/O

SK

CS

DOUT

SI

I/O

UNI/BIP

(CH1/CH2)*

SCLK

b) QSPI

c) MICROWIRE

*INDICATES THE MAX1395

Figure 7. Common Serial-Interface Connections to the

MAX1392/MAX1395