Low-EMI Clock Generator for Intel®
Mobile 133-MHz/3 SO-DIMM Chipset Systems
C9835
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07303 Rev. **
Revised April 5, 2002
Features
• Meets Intel’s Mobile 133.3MHz Chipset
• Three CPU Clocks (66.6/100/133.3 MHz, 2.5V)
• Six SDRAM Clocks, 1-DCLK (100/133.3 MHz, 3.3V)
• Seven PCI Clocks (33MHz, 3.3V), one free running
• Two IOAPIC clocks, synchronous to CPU clock (33.3
MHz, 2.5V)
• One REF Clock
• Two 48-MHz fixed non-SSCG clocks (USB and DOT)
• Three 3V66 clocks (66.6 MHz, 3.3V) ICH, HUBLINK, and
AGP memory
• One selectable frequency for VCH video channel clock
(48-MHz non-SSCG, 66.6-MHz CPU-SSCG, 3.3V)
• Power management using power-down, CPU stop, and
PCI stop pins
• Three function select pins (include test-mode select)
• Cypress Spread Spectrum for best electromagnetic
interference (EMI) reduction
• SMBUS support with readback
• 56-pin SSOP and TSSOP packages
Note:
1.
These are the frequencies that are selectable after power up using the SEL1 and SEL0 hardware pins. Other frequencies may be chosen using the devices
SMBUS interface. See the expanded frequency for a complete listing of all of the availible frequencies.
2.
Will be set to 133MHz, when SMBUS Byte3, Bit 0 is set to logic 1.
Table 1. Function Table[1]
TEST#
SEL1
SEL0
CPU(0:2)
SDRAM(0:5)
DCLK
3V66(0:2)
PCIF(1:6)
48M(0:1)
REF
IOAPIC(0:10)
0
X
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
X
1
TCLK/2
TCLK/2
TCLK/3
TCLK/6
TCLK/2
TCLK
TCLK/6
1
0
0
66.6
100.0[2]
66.6
33.3
48
14.318
33.3
1
0
1
100.0
100.0[2]
66.6
33.3
48
14.318
33.3
1
1
0
133.3
133.3
66.6
33.3
48
14.318
33.3
1
1
1
133.3
100.0[2]
66.6
33.3
48
14.318
33.3
Block Diagram
Pin Configuration
VDDC
VDDS
VDD
VD D P
VDDI
VDD
VDDS
P LL1
Ri n
i 2 c- cl k
i2 c - d a t a
I O API C
tri s ta te
PD #
s0
CPU
S DRA M
3V 66
PCI
P LL2
Ri n
48
PD #
i 2 c- cl k
i2 c - d a t a
36 p F
36 p F
3
6
3
6
2
2
1
1
VDD
XI N
XO U T
CPU( 0 : 2 )
SDRAM ( 0 : 5 )
3V 66 ( 0 : 2 )
P C I ( 1: 6)
IO A P I C ( 0 ,1 )
SD A T A
SC L K
PD#
SE L 0 , 1
TE S T #
48 M ( 0 , 1)
DC L K
RE F
V C H_ CL K
CP U_ S T P #
P C I _ ST P#
1
VDD
VDDP
PCI _ F
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
XIN
VDD
SEL 1
XO U T
VSS
VSS
3V 6 6_0
3 V 66_ 1
3 V 66 _2(A G P )
PCI_F
PCI1
VSS
PCI3
VDDP
VDD
PCI2
PCI4
PCI5
VSS
AVDD
AVSS
VSS
T EST#
CPU_ST P#
VDD
VCH_CL K
VDDS
SDRAM5
DCLK
VSS
SDRAM2
VDDS
SDRAM0
VSS
CPU2
CPU1
SDRAM4
SDRAM3
SDRAM1
VSS
VDDC
CPU0
VDDI
IO APIC1
IO APIC0
VSS
PCI6
C
9
8
3
5
25
26
27
REF
4 8M 0(U SB)
48 M 1(D O T )
28
VDD
SEL 0
SDAT A
SCLK
PD#
49
50
51
52
53
54
55
56
PCI_S T P#
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