7 / 40 page
Su
n
lus
Co
nfi
de
nti
al
p
Fo
S
NN
I
TE
CH
NO
LO
GY
&
E
CH
ND
IS
E
IN
C
SE
ON
LY
r
M
U
U
R
C A
P
Prre
elliim
miin
na
arry
y
SPHE8200A
4.SIGNAL DESCRIPTION
4.1. Pin Map
PLLVSS
FDRSET
PDRSET
PLLVDD
VREFO
FDFLT
PDFLT1
LPFNIN
LGIN1
LGIN2
HGIN
DAVDD
FEO
TEO
DAVSS
PWM_VSS
FGIN
DMEA
SC_OUT
SPDC_OUT
SC1_OUT
TRAY_OUT
PWM_VDD
TV_DAC5
VSS_TVA2
VDD_TVA2
TV_DAC4
TV_DAC3
VSS_TVA1
VDD_TVA1
TV_DAC2
TV_DAC1
VSS_TVA0
VDD_TVA0
TV_DAC0
V_REFOUT
V_FSADJ
V_BIAS
V_COMP
UA0_RX/GPIO
VDD_K6
UA0_TX/GPIO
A_XCK/GPIO
A_BCK/GPIO
VSS_K6/VSS_O7
A_LRCK/GPIO
A_DATA3/GPIO
A_DATA2/GPIO
A_DATA1/GPIO
VDD_O7
A_DATA0/GPIO
A_IEC_TX/GPIO
A_IEC_RX/GPIO
A_DATA4/GPIO
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
SPHE8200A
216 PIN LQFP
24x24mm2
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
M_CKE
VSS_K3
M_CLKO
VDD_O3
M_D8
M_D9
M_D10
M_D11
VSS_K3
M_D12
M_D13
M_D14
M_D15
VDD_K3
M_BA0
M_CS_B
M_RAS_B
M_CAS_B
VSS_O2
M_WE_B
M_D0
M_D1
M_D2
VDD_O2
M_D3
M_D4
M_D5
M_D6
M_D7
VSS_K2
CLKIN
CLKOUT
VDD_K2
VSS_PLLA
VDD_PLLA
VSS_PLLV
VDD_PLLV
R_CS3_B/GPIO
R_CS2_B/GPIO
R_OE_B/GPIO
R_CS1_B/GPIO
R_WE_B/GPIO
R_A19/GPIO
R_A18
R_A17
VSS_O1
R_A16
R_A7
R_A6
R_A5
R_A4
R_A3
R_A2
VDD_O1
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
7
OCT. 07, 2003
Preliminary Version: 0.2
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
