 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
HD6433642 Datasheet(PDF) 56 Page - Hitachi Semiconductor |
|
||||||||||||||||||||||||||||||
HD6433642 Datasheet(HTML) 56 Page - Hitachi Semiconductor |
|
|
56 / 508 page  46 Three-State Access to On-Chip Peripheral Modules: Figure 2.13 shows the operation timing in the case of three-state access to an on-chip peripheral module. T1 state Bus cycle Internal address bus Internal read signal Internal data bus (read access) Internal write signal Read data Address Internal data bus (write access) T2 state T3 state Write data SUB ø or ø Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access) 2.7 CPU States 2.7.1 Overview There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or medium- speed) mode and subactive mode. In the program halt state there are a sleep (high-speed or medium-speed) mode, standby mode, watch mode, and sub-sleep mode. These states are shown in figure 2.14. Figure 2.15 shows the state transitions. |
Similar Part No. - HD6433642 |
|
Similar Description - HD6433642 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
