DDR SDRAM

Revision 1.0 December, 2003

256MB, 512MB DDR466 Unbuffered DIMM

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Ordering Information

Operating Frequencies

Part Number

Density

Organization

Component Composition

Height

M368L3223ETM-C(L)C5

256MB

32M x 64

32Mx8( K4H560838E) * 8EA

1,250mil

M368L6423ETM-C(L)C5

512MB

64M x 64

32Mx8( K4H560838E) * 16EA

1,250mil

M381L3223ETM-C(L)C5

256MB

32M x 72

32Mx8( K4H560838E) * 9EA

1,250mil

M381L6423ETM-C(L)C5

512MB

64M x 72

32Mx8( K4H560838E) * 18EA

1,250mil

C5(DDR466@CL=3)

Speed @CL3

233MHz

CL-tRCD-tRP

3-4-4

Feature

• Power supply : Vdd: 2.6V ± 0.1V, Vddq: 2.6V ± 0.1V

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• Programmable Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333

• Programmable Burst length (2, 4, 8)

• Programmable Burst type (sequential & interleave)

• Edge aligned data output, center aligned data input

• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)

• Serial presence detect with EEPROM

• PCB : Height 1,250 (mil), single (256MB) and double(512MB) sided

• SSTL_2 Interface

184Pin Unbuffered DIMM based on 256Mb E-die (x8)