GLT4116-30J4 datasheet(8/16 Pages) ETC1

Part #	GLT4116-30J4

Description	64k x 16 CMOS Dynamic RAM with Fast Page Mode

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8

G-LINK Technology

GLT41116

July 1998 (Rev. 1)

CLK

CKE

CE

R/Wn

Don’t Care

Figure 3. NOP, STALL and DESELECT Timing

ADV/LD

BWn

ADDRESS

D/Q

A1

A2

A3

A4

A5

12

34

56789

10

Q (A2)

D (A1)

Undefined

tKHQZ

tKHQX

WRITE D(A1)

READ Q(A2)

STALL

READ Q(A1)

WRITE D(A2)

STALL

NOP

READ Q(A3)

DESELECT

Continue

DESELECT

D (A5)

NOTE:

1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE being used to create a “pause.” A WRITE is not performed during this cycle.

2. For this waveform, ZZ and OE are tied LOW.

3. CE represents three signals. When CE = 0, it represents CE = 0, CE2 = 0, CE2 = 1.

4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register.

Q (A3)

D (A4)

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