CY7C404-10DMB datasheet(8/13 Pages) CYPRESS

Part #	CY7C404-10DMB

Description	64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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8 / 13 page

CY7C401/CY7C403

CY7C402/CY7C404

8

FIFO Expansion[13, 14, 15, 16, 17]

Notes:

13. When the memory is empty, the last word read will remain on the outputs until the master reset is strobed or a new data word bubbles through to the output.

However, OR will remain LOW, indicating data at the output is not valid.

14. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data, and stays LOW

until the new data has appeared on the outputs. Anytime OR is HIGH, there is valid, stable data on the outputs.

15. If SO is held HIGH while the memory is empty and a word is written into the input, that word will ripple through the memory to the output. OR will go HIGH

for one internal cycle (at least tORL) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO,

they will line up behind the first word and will not appear on the outputs until SO has been brought LOW.

16. When the master reset is brought LOW, the outputs are cleared to LOW, IR goes HIGH and OR goes LOW. If SI is HIGH when the master reset goes HIGH,

then the data on the inputs will be written into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LOW when the master reset

is ended, then IR will go HIGH, but the data on the inputs will not enter the memory until SI goes HIGH.

17. All Cypress FIFOs will cascade with other Cypress FIFOs. However, hey may not cascade with pin-compatible FIFOs from other manufacturers.

18. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the

devices.

19. FIFOs are expandable in depth and width. However, in forming wider words two external gates are required to generate composite input and output ready

flags. This need is due to the variation of delays of the FIFOs.

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

OUTPUT READY

SHIFT IN

SHIFT OUT

INPUT READY

DATA IN

DATA OUT

MR

C401–16

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

COMPOSITE

OUTPUT READY

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

SO

OR

SI

IR

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

MR

SHIFT OUT

MR

COMPOSITE

INPUT READY

SHIFT IN

C401–17

128 x 4 Application[18]

192 x 12 Application[19]

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