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AT73C213 Datasheet(PDF) 10 Page - ATMEL Corporation |
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AT73C213 Datasheet(HTML) 10 Page - ATMEL Corporation |
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10 / 35 page  10 2744A–PMGMT–27-Jan-05 AT73C213 7.3 Data Interface Normal operation is entered by applying correct LRFS, BCLK and SDIN waveforms to the serial interface, as illustrated in Figure 7-4, Figure 7-5 and Figure 7-6. To avoid noise at the output, the reset state is maintained until proper synchronization is achieved in the serial interface. The data interface allows three different data transfer modes. See Figure 7-4, Figure 7-5 and Figure 7-6. Figure 7-4. 20-bit I2S Justified Mode Figure 7-5. 20-bit MSB Justified Mode Figure 7-6. 20-bit LSB Justified Mode The selection between modes is done using the DINTSEL<1:0> signal. The data interface always works in slave mode. This means that the LRFS and the BCLK sig- nals are provided by the host controller. In order to achieve proper operation, the LRFS and the BCLK signals must be synchronous with the MCLK master clock signal and their frequency rela- tionship must reflect the selected data mode. For example, if the data mode selected is the 20- bit MSB Justified, then the BCLK frequency must be 40 times higher than the LRFS frequency. R1 R0 L(N-1) L(N-2) L(N-3) ... L2 L1 L0 R(N-1) R(N-2) R(N-3) ... R2 R1 R0 BCLK LRFS SDIN R0 L(N-1) L(N-2) L(N-3) ... L2 L1 L0 R(N-1) R(N-2) R(N-3) ... R2 R1 R0 L(N-1) BCLK LRFS SDIN R0 L(N-1) L(N-2) ... L1 L0 R(N-1) R(N-2) ... R1 R0 L(N-1) BCLK LRFS SDIN DINTSEL <1:0> Format 00 I2S Justified 01 MSB Justified 1x LSB Justified |
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