HY57V561620T-H datasheet(8/13 Pages) HYNIX

Part #	HY57V561620T-H

Description	4Banks x 4M x 16Bit Synchronous DRAM

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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HY57V561620(L)T

Revision 1.8 / Apr.01

AC CHARACTERISTICS II

Note :

1. A new command can be given tRRC after self refresh exit.

Parameter

Symbol

-HP

-H

-8

-P

-S

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

RAS cycle time

Operation

tRC

65

-

65

-

68

-

70

-

70

-

ns

Auto Refresh

tRRC

65

-

65

-

68

-

70

-

70

-

ns

RAS to CAS delay

tRCD

20

-

20

-

20

-

20

-

20

-

ns

RAS active time

tRAS

45

100K

45

100K

48

100K

50

100K

50

100K

ns

RAS precharge time

tRP

20

-

20

-

20

-

20

-

20

-

ns

RAS to RAS bank active delay

tRRD

15

-

15

-

16

-

20

-

20

-

ns

CAS to CAS delay

tCCD

1

-

1

-

1

-

1

-

1

-

CLK

Write command to data-in delay

tWTL

0

-

0

-

0

-

0

-

0

-

CLK

Data-in to precharge command

tDPL

2

-

2

-

2

-

2

-

2

-

CLK

Data-in to active command

tDAL

5

-

5

-

5

-

4

-

4

-

CLK

DQM to data-out Hi-Z

tDQZ

2

-

2

-

2

-

2

-

2

-

CLK

DQM to data-in mask

tDQM

0

-

0

-

0

-

0

-

0

-

CLK

MRS to new command

tMRD

2

-

2

-

2

-

2

-

2

-

CLK

Precharge to data

output Hi-Z

CAS Latency = 3

tPROZ3

3

-

3

-

3

-

3

-

3

-

CLK

CAS Latency = 2

tPROZ2

-

2

-

2

-

CLK

Power down exit time

tPDE

1

-

1

-

1

-

1

-

1

-

CLK

Self refresh exit time

tSRE

1

-

1

-

1

-

1

-

1

-

CLK

1

Refresh Time

tREF

-

64

-

64

-

64

-

64

-

64

ms

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