ICM105B VGA CMOS sensor
Data Sheet V1.6, August 2002
©2000, 2001,2002 IC Media Corporation & IC Media Technology Corp
10/16/2002
web site: http://www.ic-media.com/
web site: http://www.ic-media.com.tw/
page 4
Confidential
1. Pin Assignment
Pin #
Name
Class*
Function
14
CLKSEL
D, I, N
Clock source selection. 0: internal oscillator, 1: CLKIN
11
CLKIN
D, I, N
External clock source
12
XIN
A, I
Oscillator in
13
XOUT
A, O
Oscillator out
34
PCLK
D, O
Pixel clock output
36
OEN
D, I, N
Output enable. 0: enable, 1: disable
32
SIFCID
D, I, N
Lsb of SIF slave address
33
SIFCMS
D, I, U
SIF master/slave selection. 0: slave, 1: master (auto load
from EEPROM after reset)
2
SCL
D, I/O
SIF clock
1
SDA
D, I/O
SIF data
10
POWERDN
D, I, U
Power down control, 0: power down, 1: active
16
RSET
A, I
Resistor to ground = 47 K
Ω @ 24 MHz main clock, 51
K
Ω @ 24 MHz
8
RSTN
D, I, U
Chip reset, active low
48
DOUT[7]
D, O
Data output bit 7
47
DOUT[6]
D, I/O
Data output bit 6; if pulled up/down, the initial value of
TIMING_CONTROL_LOW[2] (VSYNC polarity) is 1/0
46
DOUT[5]
D, I/O
Data output bit 5; if pulled up/down, the initial value of
TIMING_CONTROL_LOW[1] (HSYNC polarity) is 1/0
44
DOUT[4]
D, I/O
Data output bit 4; if pulled up/down, the initial value of
AD_IDL[3] (Sub ID) is 1/0
41
DOUT[3]
D, I/O
Data output bit 3; if pulled up/down, the initial value of
AD_IDL[2] (Sub ID) is 1/0
39
DOUT[2]
D, I/O
Data output bit 2; if pulled up/down, the initial value of
AD_IDL[1] (Sub ID) is 1/0
38
DOUT[1]
D, I/O
Data output bit 1; if pulled up/down, the initial value of
AD_IDL[0] (Sub ID) is 1/0
37
DOUT[0]
D, I/O
Data output bit 0; if pulled up/down, the synchronization
mode is in master/slave mode which requires HSYNC
and VSYNC operating in output/input mode
3
HSYNC
D, I/O
Horizontal sync signal
5
VSYNC
D, I/O
Vertical sync signal
35
FLASH
D, O
Flash light control
15
RAMP
A, O
Analog ramp output
7, 31
VDDA
P
Sensor analog power
9, 30
GNDA
P
Sensor analog ground
19
VDDD
P
Sensor digital power
17
GNDD
P
Sensor digital ground
4, 43
VDDK
P
Digital power
6, 45
GNDK
P
Digital ground
40
VDDO
P
Pad power
42
GNDO
P
Pad ground
18
GNDS
P
Substrate ground
Class Code: A – Analog signal, D – Digital signal, I – Input, O – Output, P – Power or ground, U – Internal
pull-up, N – Internal pull-down
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