CY7C43663AV
CY7C43643AV
CY7C43683AV
Document #: 38-06024 Rev. *C
Page 5 of 28
MBA
Port A Mailbox
Select
I
A HIGH level on MBA chooses a mailbox register for a Port A Read or Write
operation. When a Write operation is performed on Port A, a HIGH on MBA will write
the data into Mail1 register, a low on MBA will write the data into the FIFO memory.
MBB
Port B Mailbox
Select
I
A HIGH level on MBB chooses a mailbox register for a Port B Read or Write
operation. When a Read operation is performed on Port B, a HIGH level on MBB selects
data from the Mail1 register for output and a LOW level selects FIFO output register
data for output. Data can only be written into Mail2 register through Port B (MBB HIGH)
and not into the FIFO memory.
MBF1
Mail1 Register
Flag
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1
register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH
by a LOW-to-HIGH transition of CLKB when a Port B Read is selected and MBB is HIGH.
MBF1 is set HIGH following either a Master or Partial Reset.
MBF2
Mail2 Register
Flag
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH
by a LOW-to-HIGH transition of CLKA when a Port A Read is selected and MBA is HIGH.
MBF2 is set HIGH following either a Master or Partial Reset.
MRS1
Master Reset
I
A LOW on this pin initializes the FIFO Read and Write pointers to the first location
of memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1
selects the programming method (serial or parallel) and one of three programmable flag
default offsets. It also configures Port B for bus size and endian arrangement. Four
LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must
occur while MRS1 is LOW.
MRS2
Master Reset
I
A LOW on this pin initializes the Mail2 Register.
PRS
Partial Reset
I
A LOW on this pin initializes the FIFO Read and Write pointers to the first location
of memory and sets the Port B output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or
parallel), and programmable flag settings are all retained.
RT
Retransmit
I
A LOW strobe on this pin will retransmit the data in the FIFO. This is achieved by
bringing the Read pointer back to location zero. The user will still need to preform Read
operations to retransmit the data. Retransmit function applies to CY standard mode only.
SIZE
Bus Size Select
I
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW
on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and
BE to select the bus size and endian arrangement for Port B. The level of SIZE must be
static throughout device operation.
SPM
Serial
Programming
I
A LOW on this pin selects serial programming of partial flag offsets. A HIGH on
this pin selects parallel programming or default offsets (8, 16, or 64).
W/RA
Port A
Write/Read
Select
I
A HIGH selects a Write operation and a LOW selects a Read operation on Port A
for a LOW-to-HIGH transition of CLKA. The A0–35 outputs are in the high-impedance
state when W/RA is HIGH.
W/RB
Port B
Write/Read
Select
I
A LOW selects a Write operation and a HIGH selects a Read operation on Port B
for a LOW-to-HIGH transition of CLKB. The B0–35 outputs are in the high-impedance
state when W/RB is LOW.
Pin Definitions (continued)
Signal Name
Description
I/O
Function
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
