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3
EDS-104432 Rev 3
Advanced Information
SVG-2066 500MHz-2200MHz 6-Bit VGA
Table 2: Parallel Mode Truth table (S-P=0)
Attenuation State
P0.5
P1
P2
P4
P8
P16
Reference
0
0
0
0
0
0
0.5 dB
1
0
0
0
0
0
1 dB
0
1
0
0
0
0
2 dB
0
0
1
0
0
0
4 dB
0
0
0
1
0
0
8 dB
0
0
0
0
1
0
16 dB
0
0
0
0
0
1
31.5 dB
1
1
1
1
1
1
Table 4: Power Up Truth Table for Parallel Mode (S-P=0)
Attenuation State
LE
U1
U2
Reference
0
0
0
8 dB
0
1
0
16 dB
0
0
1
31 dB
0
1
1
Defined by P0.5 Thru P16
1
Not
Applicable
Not
Applicable
Parameter
Symbol
Unit
Min
Max
Serial data delay before
clock rising edge
TD1
nS
10
Serial data hold after
clock falling edge
TD2
nS
10
LE delay after last clock
falling edge
TD3
nS
10
LE minimum pulse
width
TD4
nS
30
Serial data clock freq
FCLK
MHz
20
Serial clock high time
TCLKH
nS
30
Serial clock low time
TCLKL
nS
30
Table 3: Serial Mode Timing Specifications
LE
Data
P0.5 thru
P16
TD6
TD7
TD5
Figure 1: Parallel Mode Timing Diagram (S-P=0)
Figure 2: Serial Mode Timing Diagram (S-P=1)
Parameter
Symbol
Unit
Min
Max
LE minimum pulse
width
TD6
nS
10
Delay set up time
before rising LE edge
TD5
nS
10
Data hold after falling
edge of LE
TD7
nS
10
Table 1: Parallel Mode Timing Specifications (S-P=0)
MSB
LSB
CLK
LE
DATA
TD1
TD2
TD3
TD4
8dB
4dB
2dB
1dB
16dB
0.5dB
Note: Serial mode power up (S-P=1) state is
defined by the parallel input logic shown in
Table 2.
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