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KESRX05KG1T Datasheet(PDF) 10 Page - Zarlink Semiconductor Inc

Part # KESRX05KG1T
Description  260 to 470MHz ASK Receiver with Power Down
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

KESRX05KG1T Datasheet(HTML) 10 Page - Zarlink Semiconductor Inc

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9
KESRX05
NOTES (continued)
7. In-band interference rejection for an unmodulated interfering signal at 100kHz low side from the wanted modulated signal at 433.92MHz to
achieve a Bit Error Rate = 0·01. Figure 6 illustrates a suitable test set-up for measuring the interference rejection and selectivity of the receiver.
Wanted signal = 290dBm at 433·92MHz (2kb/. 50% duty cycle), interfering signal = 278dBm at 433·82MHz. (unmodulated). Interference rejection
typically equals +12dBm i.e. in-band interfering signal is 12dBm above the wanted signal level at -90dBm.
8. Actual intermediate frequency determined by choice of crystal and external ceramic filter.
9. For temperatures between 85
°C and 105°C the maximum frequency of operation of the VCO local oscillator must be limited to 470MHz. The
recommended components to limit the maximum free running frequency of the VCO to less than 470MHz, for an operating supply range of
5V65%, are:
The component values recommended in Tables 5 and 6 are to allow the KESRX05 to operate below VCC = 3V by maintaining the PLL lock voltage
at approximately 1·5V (VCC/2) so that the VCO maximum free running frequency can exceed 470MHz. Thus, the recommended VCO component
values for D!, C11, C18 and L2 given in Tables 5 and 6 cannot be used at temperatures above 85
°C.
10.Sensitivity is defined as the average signal level measured at the input necessary to achieve a bit error rate of 0·01 where the input signal is a
return to zero pulse with an average duty cycle of 50%, 2kb/s data rate. Equivalent to 2109dBm for a 50
Ω input impedance. Does not include the
insertion loss of a front end SAW filter at the R F input but does include the IF filter of 50kHz 3dB bandwidth and a data filter bandwidth of 5kHz.
The results shown in Figure 20 and in the AC Electrical Characteristics (1) on page 7 are with the simple LC circuit L5//C7 tuned correctly to
10·7MHz.
11. This parameter is not 100% tested by production.
Ident
Value
Tolerance
D1
BB833
69%
C11
6·8pF
60·1pF
C18
10pF
60·1pF
L2
39nH
62%
FUNCTIONAL DESCRIPTION
Power Down
The PD pin, a tristate input, provides a 2-stage power down
for the receiver. The receiver is fully operational when the
pin is held high and is fully powered down when the pin is
taken to ground as shown in Table 2.
Status
Pin 25
Receiver powered down
Crystal oscillator running
Receive mode
Low (0V)
VCC/2
High (VCC)
PD0
PD1
PD2
Table 2
PD0 = Low
None of the receiver circuits are functional. Current ICC2,
is reduced to its lowest level of ,50
µA (VCC applied). A
longer settling time (tS2) is required to restore full
performance after switching to receive mode PD0 to PD2
(Figures 7, 17 and 18). The settling time (time to valid data)
of the receiver can be improved by maintaining the
oscillation of the crystal in PD0 mode by placing a 200K
resistor in parallel with C14. The addition of this resistor
will increase the current consumption of the receiver by
approximately 20
µA (see Table 1, pin 23).
PD1 = VCC/2 or High-Z source (CMOS tristate)
A non-receiving state with some critical circuits running
including the crystal oscillator. Current consumption ICC1,
is reduced to about 330
µA. When switching to the receive
state, PD1 to PD2 (Figures 7, 17 and 18), data can start to
be recovered within 1ms (tS2) for signals close to maximum
sensitivity.
PD2 = High
The receiver is fully functional and ready to receive data.
RF Down-Converter
An internal RF amplifier is designed to interface directly to
an antenna or to an input SAW filter with a maximum
insertion loss of 3dB. The RF amplifier gain is about 1 3dB
at 460MHz when matched into the mixer, while the RF
amplifer noise figure is about 4·5dB when fed from a 50
source. The internal RF amplifier feeds a double balanced
mixer through an external impedance matching circuit,
RFOP to MIXIP.
The AGC circuit monitors the mixer signal output level.
Control is fed back, applying AGC to the RF amplifier to
prevent overloading in the mixer and the generation of
unwanted distortion products. This also has the effect of
reducing the RSSI characteristic slope and extending its
range of operation by more than 20dB at high signal levels
(Figure 13).
The AGC circuit also applies mixer booster current to
improve the linearity of the mixer at high signal levels. This
can be confirmed by monitoring the current consumption
of the receiver with applied RF signal level (Figure 16).
The AGC circuit comes into operation at mixer output
signals greater than approximately 225dBm and reduces
the RF amplifer gain by 6dB at an input signal level of
approximaely 230dBm. Since the AGC operates on the
mixer output signal level then the exact point where the
AGC comes into opera tion depends on the RF amplifer to
mixer matching circuits and RF amplifer gain.
IF Interface
Unlike KESRX01 there is no internal integrated IF filter.
This is to provide a more flexible design and allows the
system designer to use a low IF or high IF up to 15MHz.
Typically, a 10·7MHz ceramic IF filter connected between
IFOUT and IFIN would be used together with an input RF
SAW filter to give very good image channel rejection. The


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