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CY7C138
CY7C139
9
Notes:
26. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH
27. Semaphores are reset (available to both ports) at cycle start.
28. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
Switching Waveforms (continued)
MATCH
C138-14
tSPS
A0L–A2L
MATCH
R/WL
SEML
A0R–A2R
R/WR
SEMR
Timing Diagram of Semaphore Contention [26, 27, 28]
VALID
tDDD
tWDD
MATCH
MATCH
R/WR
DATA INR
DATAOUTL
C138-15
tWC
ADDRESS R
tPWE
VALID
tSD
tHD
ADDRESSL
tPS
tBLA
tBHA
tBDD
BUSYL
Timing Diagram of Read with BUSY (M/S=HIGH)
[20]
tPWE
R/W
BUSY
tWB
tWH
C138-16
Write Timing with Busy Input (M/S=LOW)