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COPCH682C Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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COPCH682C Datasheet(HTML) 11 Page - National Semiconductor (TI) |
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11 / 31 page  Typical Performance Characteristics (−40˚C ≤ T A ≤ +85˚C) (Continued) Pin Descriptions V CC and GND are the power supply pins. CKI is the clock input. This can come from an external source, a R/C generated oscillator or a crystal (in conjunc- tion with CKO). See Oscillator description. RESET is the master reset input. See Reset description. PORT I is an 8-bit Hi-Z input port. The 28-pin device does not have a full complement of Port I pins. The unavailable pins are not terminated i.e., they are floating. A read operation for these unterminated pins will return unpredictable values. The user must ensure that the software takes this into ac- count by either masking or restricting the accesses to bit operations. The unterminated Port I pins will draw power only when addressed. PORT L is an 8-bit I/O port. PORT C is a 4-bit I/O port. Three memory locations are allocated for the L, G and C ports, one each for data register, configuration register and the input pins. Reading bits 4–7 of the C-Configuration reg- ister, data register, and input pins returns undefined data. There are two registers associated with the L and C ports: a data register and a configuration register. Therefore, each L and C I/O bit can be individually configured under software control as shown below: Con- fig. Data Ports L and C Setup 0 0 Hi-Z Input (TRI-STATE Output) 0 1 Input with Pull-Up (Weak One Output) 1 0 Push-Pull Zero Output 1 1 Push-Pull One Output On the 28-pin part, it is recommended that all bits of Port C be configured as outputs. PORT G is an 8-bit port with 6 I/O pins (G0–G5) and 2 input pins (G6, G7). All eight G-pins have Schmitt Triggers on the inputs. There are two registers associated with the G port: a data register and a configuration register. Therefore, each G port bit can be individually configured under software control as shown below: Con- fig. Data Port G Setup 0 0 Hi-Z Input (TRI-STATE Output) 0 1 Input with Pull-Up (Weak One Output) 1 0 Push-Pull Zero Output 1 1 Push-Pull One Output Since G6 and G7 are input only pins, any attempt by the user to configure them as outputs by writing a one to the configu- ration register will be disregarded. Reading the G6 and G7 configuration bits will return zeros. The device will be placed in the HALT mode by writing to the G7 bit in the G-port data register. Six pins of Port G have alternate features: G0 INTR (an external interrupt) G3 TIO (timer/counter input/output) G4 SO (MICROWIRE serial data output) G5 SK (MICROWIRE clock I/O) G6 SI (MICROWIRE serial data input) G7 CKO crystal oscillator output (selected by mask option) or HALT restart input (general purpose input) Pins G1 and G2 currently do not have any alternate func- tions. PORT D is an 8-bit output port that is preset high when RESET goes low. Care must be exercised with the D2 pin operation. At RESET, the external loads on this pin must ensure that the output voltages stay above 0.9 V CC to pre- vent the chip from entering special modes. Also, keep the external loading on D2 to less than 1000 pF. Functional Description Figure 1 shows the block diagram of the internal architec- ture. Data paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. ALU AND CPU REGISTERS The ALU can do an 8-bit addition, subtraction, logical or shift operation in one cycle time. There are five CPU registers: A is the 8-bit Accumulator register PU is the upper 7 bits of the program counter (PC) PL is the lower 8 bits of the program counter (PC) Port D Sink Current DS010802-22 www.national.com 11 |
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