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COP87L22CJM-2N Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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COP87L22CJM-2N Datasheet(HTML) 11 Page - National Semiconductor (TI) |
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11 / 32 page  Functional Description (Continued) MICROWIREPLUS MICROWIREPLUS is a serial synchronous bidirectional communications interface The MICROWIREPLUS capabil- ity enables the device to interface with any of National Semiconductor’s MICROWIRE peripherals (ie AD con- verters display drivers EEPROMS etc) and with other mi- crocontrollers which support the MICROWIREPLUS inter- face It consists of an 8-bit serial shift register (SIO) with serial data input (SI) serial data output (SO) and serial shift clock (SK) Figure 6 shows the block diagram of the MICRO- WIREPLUS interface TLDD11208 – 8 FIGURE 6 MICROWIREPLUS Block Diagram The shift clock can be selected from either an internal source or an external source Operating the MICROWIRE PLUS interface with the internal clock source is called the Master mode of operation Operating the MICROWIRE PLUS interface with an external shift clock is called the Slave mode of operation The CNTRL register is used to configure and control the MICROWIREPLUS mode To use the MICROWIREPLUS the MSEL bit in the CNTRL register is set to one The SK clock rate is selected by the two bits SL0 and SL1 in the CNTRL register Table III details the different clock rates that may be selected TABLE III SL1 SL0 SK Cycle Time 00 2tc 01 4tc 1x 8tc where tc is the instruction cycle time MICROWIREPLUS OPERATION Setting the BUSY bit in the PSW register causes the MI- CROWIREPLUS arrangement to start shifting the data It gets reset when eight data bits have been shifted The user may reset the BUSY bit by software to allow less than 8 bits to shift The device may enter the MICROWIREPLUS mode either as a Master or as a Slave Figure 7 shows how two device microcontrollers and several peripherals may be interconnected using the MICROWIREPLUS arrangement Master MICROWIREPLUS Operation In the MICROWIREPLUS Master mode of operation the shift clock (SK) is generated internally by the device The MICROWIREPLUS Master always initiates all data ex- changes (Figure 7) The MSEL bit in the CNTRL register must be set to enable the SO and SK functions on the G Port The SO and SK pins must also be selected as outputs by setting appropriate bits in the Port G configuration regis- ter Table IV summarizes the bit settings required for Master mode of operation SLAVE MICROWIREPLUS OPERATION In the MICROWIREPLUS Slave mode of operation the SK clock is generated by an external source Setting the MSEL bit in the CNTRL register enables the SO and SK functions on the G Port The SK pin must be selected as an input and the SO pin selected as an output pin by appropriately setting up the Port G configuration register Table IV summarizes the settings required to enter the Slave mode of operation TLDD11208 – 23 FIGURE 7 MICROWIREPLUS Application http www nationalcom 11 |
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