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ISPLSI1032EA-125LT100 Datasheet(PDF) 8 Page - Lattice Semiconductor |
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ISPLSI1032EA-125LT100 Datasheet(HTML) 8 Page - Lattice Semiconductor |
8 / 16 page 8 Specifications ispLSI 1032EA GRP Delay, 32 GLB Loads tiobp 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Table 2-0036A/1032EA Inputs UNITS -170 MIN. MIN. MAX. MAX. DESCRIPTION # 2 PARAM. 22 I/O Register Bypass ns tiolat 23 I/O Latch Delay ns tgrp32 33 ns GLB t1ptxor 36 1 ProductTerm/XOR Path Delay ns t20ptxor 37 20 Product Term/XOR Path Delay ns txoradj 38 XOR Adjacent Path Delay ns tgbp 39 GLB Register Bypass Delay ns tgsu 40 GLB Register Setup Time before Clock ns tgh 41 GLB Register Hold Time after Clock ns tgco 42 GLB Register Clock to Output Delay ns 3 tgro 43 GLB Register Reset to Output Delay ns tptre 44 GLB Product Term Reset to Register Delay ns tptoe 45 GLB Product Term Output Enable to I/O Cell Delay ns tptck 46 GLB Product Term Clock Delay ns ORP GRP t4ptbpc 34 4 ProductTerm Bypass Path Delay (Combinatorial) ns t4ptbpr 35 4 Product Term Bypass Path Delay (Registered) ns torp 48 ORP Delay ns torpbp 49 ORP Bypass Delay ns tiosu 24 I/O Register Setup Time before Clock ns tioh 25 I/O Register Hold Time after Clock ns tioco 26 I/O Register Clock to Out Delay ns tior 27 I/O Register Reset to Out Delay ns tdin 28 Dedicated Input Delay ns tgrp16 32 GRP Delay, 16 GLB Loads ns tgrp8 31 GRP Delay, 8 GLB Loads ns tgrp4 30 GRP Delay, 4 GLB Loads ns tgrp1 29 GRP Delay, 1 GLB Load ns -200 — — — — — — — — — — — — — 0.3 1.0 1.2 — — 3.0 0.0 — — — — — — — 0.3 4.0 2.9 1.6 1.6 1.6 0.8 1.1 4.2 2.2 2.3 1.4 1.5 — — 2.2 0.6 0.1 — — 4.0 4.0 1.1 2.1 1.7 1.5 1.3 — — — — — — — — — — — — — 0.3 2.0 1.7 — — 3.0 0.0 — — — — — — — 0.3 4.0 3.0 2.3 2.2 2.2 1.0 1.4 4.7 2.7 3.6 2.1 2.0 — — 2.7 tgfb 47 GLB Feedback Delay ns — 0.1 — 0.1 1.0 0.1 — — 4.6 4.6 1.8 2.2 1.8 1.6 1.4 Internal Timing Parameters1 |
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