4 / 6 page
PRELIMINARY
CY24141-3
Document #: 38-07324 Rev. **
Page 4 of 6
Test Circuit
DC
Output Duty Cycle
Duty Cycle is defined in Figure 1, 50% of VDD
45
50
55
%
t3
Rising Edge Slew Rate
Output Clock Rise Time, 20%–80% of VDD/ VDDL = 2.5V
0.8
1.4
V/ns
t4
Falling Edge Slew Rate
Output Clock Fall Time, 80%–20% of VDD/ VDDL = 2.5V
0.8
1.4
V/ns
t5
PLL Lock Time
3ms
AC Electrical Characteristics (VDD = 3.15V–3.6V) (continued)
Parameter[3]
Description
Conditions
Min.
Typ. Max.
Unit
0.1
µF
AVDD
0.1
µF
VDD
CLK out
CLOAD
GND
OUTPUTS
t1
t2
CLK
50%
Figure 1. Duty Cycle Definition; DC = t2/t1
t3
CLK
80%
20%
t4
Figure 2. Rise and Fall Time Definitions
VDD
80%
Stable @ ±0.1% frequency
t5
Figure 3. PLL Lock Time
t9A
t9B
Figure 4. Cycle-Cycle Jitter
t10
t10
...
...
Figure 5. 1000-Cycle Jitter
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
Operating Voltage
CY24141ZC-3
Z16
16-TSSOP
Commercial
3.3V
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
