C9827H
High Performance Pentium® 4 Clock Synthesizer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 2 of 25
Approved Product
Pin Description
PIN
NAME
PWR
I/O
Description
2
XIN
I
Oscillator Buffer Input. Connect to a crystal or to an external clock.
3
XOUT
VDD
O
Oscillator Buffer Output. Connect to a crystal. Do not connect when an
external clock is applied at XIN.
52, 51, 49,
48, 45, 44
CPU, CPU/
(0:2)
VDD
O
Differential host output clock pairs. See the frequency table on page
one of this data sheet for frequencies and functionality.
10, 11, 12,
13, 16, 17, 18
PCI(0:6)
VDDP
O
PCI Clock Outputs. Are synchronous to 66IN or 3V66 clock. See
Frequency Table on page one of this data sheet.
5, 6, 7
PCIF (0:2)
VDD
O
33Mhz PCI clocks, which are
÷2 copies of 66IN or 3V66 clocks, may be
free running (not stopped when PCI_STP# is asserted low) or may be
stoppable depending on the programming of SMBus register Byte3,
Bits (3:5).
56
REF
VDD
O
Buffered Output copy of the device’s XIN clock.
42
IREF
VDD
I
Current reference programming input for CPU buffers. A resistor is
connected between this pin and VSSIREF. See CPU Clock current
Select Table in page 18 of this data sheet.
28
VTT_PG#
VDD
I
Qualifying input that latches S (0:2) and MULT0. When this input is at a
logic low, the S (0:2) and MULT0 are latched
39
48MUSB
VDD48
O
Fixed 48MHz USB Clock Outputs.
38
48MDOT
VDD48
O
Fixed 48MHZ DOT Clock Outputs.
33
3V66_0
VDD
O
3.3 Volt 66 MHz fixed frequency clock.
35
3V66_1/VCH
VDD
O
3.3 volt clock selectable with SMBus byte0, Bit5, when Byte5, Bit5.
When Byte 0 Bit 5 is at a logic 1, then this pin is a 48M output clock.
When byte0, Bit5 is a logic 0, then this is a 66M output clock (default).
25
PD#
VDD
I
PU
This pin is a power down mode pin. A logic low level causes the device
to enter a power down state. All internal logic is turned off except for the
SMBus logic. All output buffers are stopped. See the Power Down
section of this data sheet.
43
MULT0
I
PU
Programming input selection for CPU clock current multiplier. See CPU
Clock Current Select Function Table.
55, 54
S(0,1)
I
I
Frequency Select Inputs. See Frequency Table on page 1.
29
SDATA
I
I
Serial Data Input. Conforms to the SMBus specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an
open drain output when acknowledging or transmitting data. See
application note AN-0022
30
SCLK
I
I
Serial Clock Input. Conforms to the SMBus specification. See
application note AN-0022.
40
S2
VDD
I
T
Frequency Select input. See Frequency Table on page 1. This is a Tri
level input that is driven high, low or driven to a intermediate level.
34
PCI_STP#
VDD
I
PU
PCI Clock Disable Input. When asserted low, PCI (0:6) clocks are
synchronously disabled in a low state. This pin does not effect PCIF
(0:2) clocks’ outputs if they are programmed to be PCIF clocks via the
device’s SMBus interface.
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