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MP7612AP Datasheet(PDF) 8 Page - Exar Corporation |
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MP7612AP Datasheet(HTML) 8 Page - Exar Corporation |
8 / 20 page MP7612 8 Rev. 3.00 The MP7612 is equipped with a serial data (3-wire standard) µ-processor logic interface to reduce pin count, package size, and board wire (space). If the LD signal is high, the CLK signal loads the digital input bits (SDI) into the shift register (4 bits ad- dress A3 to A0 plus 12 bits data DB11 to DB0 for the MP7612). The LD signal going low loads the data into the selected DAC. The LD signal going low also disables the serial data (SDI), out- put (SDO 3-stated) and the CLK input. This design tremen- dously reduces digital noise and glitch transients into the DACs due to free running CLK and SDI. Note also that the preset sig- nal (RST) resets all analog outputs to 0 volt regardless of digital inputs. A3 A2 A1 A0 XX X X 1 1 DAC 0 0 0 0 1 DAC 1 0 0 1 0 DAC 2 0 0 1 1 DAC 3 0 1 0 0 DAC 4 0 1 0 1 DAC 5 0 1 1 0 DAC 6 0 1 1 1 DAC 7 1 0 0 0 X X X X X X X X 1 1 1 1 1 1 1 1 XX X X X X 0 11 1 0 11 1 1 1 1 Function LD CLK RST Shift Data In and Out 0 →1 Repeat Load DACs 1 →0 1 →0 1 →0 1 →0 1 →0 1 →0 1 →0 Reset all DACs to 0 V No Operation No Operation Table 1. Digital Function Truth Table Serial In/Serial Out 1 →0 X X X X X SDI Data Input Valid X X X X X X X X X X X SDO Data Output Valid Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 0 0 0 No Operation Stop Shifting Data In and Out XX X X 0 1 Hi-Z XX X No Operation Note: For timing information see Electrical Characteristics |
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