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Stock No. 23005-07 6/99
5
NanoAmp Solutions
EM128C08
TABLE 8: Timing - EM128C08-10 Version
FIGURE 3: Read Cycle Timing (WE = VIH)
Item
Symbol
1.5 to 3.6 V 1.8 to 3.6 V
2.7 to 3.6 V
3.0 to 3.6 V
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
500
300
120
100
ns
Address Access Time
tAA
500
300
120
100
ns
Chip Enable Access Time
tCE
500
300
120
100
ns
Output Enable to Valid Output
tOE
100
60
25
25
ns
Chip Enable to Low-Z output
tLZ
0
0
0
0
ns
Output Enable to Low-Z Output
tOLZ
0
0
0
0
ns
Chip Disable to High-Z Output
tHZ
0
100
0
60
0
25
0
25
ns
Output Disable to High-Z Output
tOHZ
0
100
0
60
0
25
0
25
ns
Output Hold from Address Change
tOH
10
10
10
10
ns
Write Cycle Time
tWC
500
300
120
100
ns
Chip Enable to End of Write
tCW
500
300
120
100
ns
Address Valid to End of Write
tAW
500
300
120
100
ns
Address Set-Up Time
tAS
0
0
0
0
ns
Write Pulse Width
tWP
300
100
50
40
ns
Write Recovery Time
tWR
0
0
0
0
ns
Write to High-Z Output
tWHZ
0
100
0
60
0
25
0
25
ns
Data to Write Time Overlap
tDW
300
80
40
30
ns
Data Hold from Write Time
tDH
0
0
0
0
ns
End Write to Low-Z Output
tOW
10
10
10
10
ns
A0-A16
CE1/CE2
OE
D0-D7
tRC
tCE
tOE
tOHZ
tHZ
tAA
Data Valid
tLZ
tOH
tOLZ
Enable Valid
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