HY27LF161G2M-TPMS datasheet(1/48 Pages) HYNIX

Part #	HY27LF161G2M-TPMS

Description	1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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Rev 0.7 / Apr. 2005

1

Preliminary

HY27UF(08/16)1G2M Series

HY27SF(08/16)1G2M Series

1Gbit (128Mx8bit / 64Mx16bit) NAND Flash

Document Title

1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory

Revision History

Revision

No.

History

Draft Date

Remark

0.0

1) Initial Draft.

Aug. 2004

Preliminary

0.1

1) Correct Fig.10 Sequential out cycle after read

2) Add the text to Fig.1, Table.1, Table.2

- text : IO15 - IO8 (x16 only)

3) Delete ‘3.2 Page program NOTE 1.

- Note : if possible it is better to remove this constrain

4) Change the text ( page 10,13, 45)

- 2.2 Address Input : 28 Addresses -> 27 Addresses

- 3.7 Reset : Fig.29 -> Fig.30

- 5.1 Automatic page read after power up : Fig.30 -> Fig.29

5) Add 5.3 Addressing for program operation & Fig.34

Sep. 2004

Preliminary

0.2

1) Change TSOP, WSOP, FBGA package dimension & figures.

- Change TSOP, WSOP, FBGA package mechanical data

- Change FBGA thickness (1.2 -> 1.0 mm)

2) Correct TSOP, WSOP Pin configurations.

- 38th NC pin has been changed Lockpre(figure 3,4)

3) Edit figure 15,19 & table 4

4) Add Bad Block Management

5) Change Device Identifier 3rd Byte

- 3rd Byte ID is changed. (reserved -> don't care)

- 3rd Byte ID table is deleted.

Oct. 2004

Preliminary

0.3

1) Add Errata

2) LOCKPRE is changed to PRE.

- Texts, Table, Figures are changed.

3) Add Note.4 (table.14)

4) Block Lock Mechanism is deleted.

- Texts, Table, figures are deleted.

5) Add Application Note(Power-On/Off Sequence & Auto Sleep mode.)

- Texts & Figures are added.

6) Edit the figures. (#10~25)

Nov.29 2004

Preliminary

0.4

1) Change AC characteristics(tREH)

before: 20ns -> after: 30ns

2) Edit Note.1 (page. 21)

3) Edit the Application note 1,2

4) Edit The Address cycle map (x8, x16)

Jan.19 2005

Preliminary

tCLS tCLH

tWP

tALS tALH

tDS

tWC

tR

Specification

0

10

25

0

10

20

50

25

Relaxed value

5

15

40

5

15

25

60

27

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