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M5M465405BTP-5S Datasheet(PDF) 10 Page - Mitsubishi Electric Semiconductor |
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M5M465405BTP-5S Datasheet(HTML) 10 Page - Mitsubishi Electric Semiconductor |
10 / 39 page MITSUBISHI ELECTRIC Jun. 1999 EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs (Rev. 1.1) M5M467405/465405BJ,BTP -5,-6,-5S,-6S M5M467805/465805BJ,BTP -5,-6,-5S,-6S M5M465165BJ,BTP -5,-6,-5S,-6S TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and EDO Mode Cycles) (Ta=0 70 , Vcc=3.3 0.3V, Vss=0V, unless otherwise noted See notes 14,15) C Read and Refresh Cycles Parameter Symbol Limits Unit Note 22: Either tRCH or tRRH must be satisfied for a read cycle. Read cycle time RAS low pulse width CAS low pulse width tRC 0 tRAS tCAS tCSH tRSH tRCS CAS hold time after RAS low Read Setup time before CAS low Read hold time after CAS high (Note 22) tRCH tRRH (Note 22) 0 tRAL tORH RAS hold time after CAS low Read hold time after RAS high Column address to RAS hold time RAS hold time after OE low 10000 10000 10000 10000 84 50 8 35 13 0 25 13 0 0 104 60 10 40 15 0 30 15 tCAL Column address to CAS hold time 13 18 ns ns ns ns ns ns ns ns Min Max Min Max ns ns ns tOCH 13 15 ns CAS hold time after OE low ± Note 14: The timing requirements are assumed tT =2ns. 15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. 17: tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA. 18: tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC. 19: Either tDZC or tDZO must be satisfied. 20: Either tRDD or tCDD or tODD or tWED must be satisfied. 21: tT is measured between VIH(min) and VIL(max). ≥ ≥ ≥ ≤ ~ Parameter Symbol Limits Unit M5M46X405B-5,5S M5M46X805B-5,5S M5M465165B-5,5S M5M46X405B-6,6S M5M46X805B-6,6S M5M465165B-6,6S Refresh cycle time tREF 64 64 ms Min Max Min Max RAS high pulse width Delay time, RAS low to CAS low tRP tRCD tCRP tRPC tCPN Delay time, CAS high to RAS low Delay time, RAS high to CAS low CAS high pulse width (Note21) (Note16) (Note17) (Note18) 45 30 0 40 13 50 14 5 10 12 10 10 0 0 1 37 25 0 30 10 50 14 5 8 10 8 8 0 0 1 tRAD tASR tASC tRAH tCAH tT Column address delay time from RAS low Row address setup time before RAS low Column address setup time before CAS low Row address hold time after RAS low Column address hold time after CAS low Transition time (Note19) (Note20) (Note19) (Note20) Delay time, data to CAS low Delay time, data to OE low Delay time, CAS high to data Delay time, OE high to data tDZC tDZO tCDD tODD 0 0 0 0 15 13 15 13 (Note20) Delay time, RAS high to data tRDD 15 13 ns ns ns ns ns ns ns ns ns 128 128 ms Refresh cycle time (S-version only) tREF ns ns ns ns ns ns ns ns 15 13 (Note20) Delay time, W low to data tWED 10 M5M46X405B-5,5S M5M46X805B-5,5S M5M465165B-5,5S M5M46X405B-6,6S M5M46X805B-6,6S M5M465165B-6,6S |
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