BUF12800AIPWP datasheet(6/20 Pages) BURR-BROWN

Part #	BUF12800AIPWP

Description	REFERENCE VOLTAGE GENERATOR for LCD GAMMA CORRECTION

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Manufacturer	BURR-BROWN [Burr-Brown (TI)]

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BUF12800

SBOS315 − DECEMBER 2004

www.ti.com

6

TWO-WIRE BUS OVERVIEW

The BUF12800 communicates through an industry-stan-

dard, two-wire interface to receive data in slave mode. This

standard uses a two-wire, open-drain interface that

supports multiple devices on a single bus. Bus lines are

driven to a logic low level only. The device that initiates the

communication is called a master, and the devices

controlled by the master are slaves. The master generates

the serial clock on the clock signal line (SCL), controls the

bus access, and generates the START and STOP

conditions.

To address a specific device, the master initiates a START

condition by pulling the data signal line (SDA) from a HIGH

to LOW logic level while SCL is HIGH. All slaves on the bus

shift in the slave address byte, with the last bit indicating

whether a read or write operation is intended. During the

ninth clock pulse, the slave being addressed responds to

the master by generating an Acknowledge and pulling

SDA LOW.

Data transfer is then initiated and 8 bits of data are sent

followed by an Acknowledge Bit. During data transfer,

SDA must remain stable while SCL is HIGH. Any change

in SDA while SCL is HIGH will be interpreted as a START

or STOP condition.

Once all data has been transferred, the master generates

a STOP condition indicated by pulling SDA from LOW to

HIGH while SCL is HIGH.

The BUF12800 can act only as a slave device; therefore,

it never drives SCL. SCL is an input only for the BUF12800.

ADDRESSING THE BUF12800

The address of the BUF12800 is 111010x, where x is the

state of the A0 pin. When the A0 pin is LOW, the device will

acknowledge on address 74h (1110100). If the A0 pin is

HIGH, the device will acknowledge on address 75h

(1110101).

Other valid addresses are possible through a simple mask

change. Contact your TI representative for information.

DATA RATES

The two-wire bus operates in one of three speed modes:

D Standard: allows a clock frequency of up to 100kHz;

D Fast: allows a clock frequency of up to 400kHz; and

D High-speed mode (also called Hs mode): allows a

clock frequency of up to 3.4MHz.

The BUF12800 is fully compatible with all three modes. No

special action is required to use the device in Standard or

Fast modes, but High-speed mode must be activated. To

activate High-speed mode, send a special address byte of

00001xxx, with SCL = 400kHz, following the START

condition; where xxx are bits unique to the Hs-capable

master, which can be any value. The BUF12800 will

respond to the High-speed mode command regardless of

the value of these last three bits. This byte is called the Hs

master code. (Note that this is different from normal

address bytes—the low bit does not indicate read/write

status.) The BUF12800 will not acknowledge this byte; the

communication protocol prohibits acknowledgment of the

Hs master code. On receiving a master code, the

BUF12800 will switch on its Hs mode filters, and

communicate at up to 3.4MHz. Additional high-speed

transfers may be initiated without the Hs mode byte by

generating a repeat START without a STOP. The

BUF12800 will switch out of Hs mode at the first occurence

of a STOP condition.

GENERAL CALL RESET AND POWER-UP

The BUF12800 responds to a General Call Reset, which

is an address byte of 00h (0000 0000) followed by a data

byte of 06h (0000 0110). The BUF12800 acknowledges

both bytes. Upon receiving a General Call Reset, the

BUF12800 performs a full internal reset, as though it had

been powered off and then on. It always acknowledges the

General Call address byte of 00h (0000 0000), but does

not acknowledge any General Call data bytes other than

06h (0000 0110).

When the BUF12800 powers up, it automatically performs

a reset. As part of the reset, the BUF12800 is configured

based on the codes shown in Table 1.

Table 1. BUF12800 Reset Codes

RESET CODES

BUFFER

(Hex)

(Decimal)

(Binary)

BUFFER A

Code 3E0

992

11 1110 0000

BUFFER B

Code 360

864

11 0110 0000

BUFFER C

Code 320

800

11 0010 0000

BUFFER D

Code 300

768

11 0000 0000

BUFFER E

Code 2C0

704

10 1100 0000

BUFFER F

Code 240

576

10 0100 0000

BUFFER G

Code 1C0

448

01 1100 0000

BUFFER H

Code 140

320

01 0100 0000

BUFFER I

Code 100

256

01 0000 0000

BUFFER J

Code 0E0

224

00 1110 0000

BUFFER K

Code 0A0

160

00 1010 0000

BUFFER L

Code 020

32

00 0010 0000

Buffer values are calculated using Equation 1:

V

OUT +

V

REFH * VREFL

1024

decimal value of code

) V

REFL

Other

reset

values

are

available

as

a

custom

modification—contact your TI representative for details.

OUTPUT VOLTAGE

Buffer output values are determined by the reference

voltages (VREFH and VREFL) and the decimal value of the

binary input code used to program that buffer. The value is

calculated using Equation 1; see the Reset and Power-Up

section. The valid voltage ranges for the reference

voltages are:

4V

v V

REFH v VS * 0.2V and 0.2V v VREFL v VS * 4V

The BUF12800 outputs are capable of a full-scale voltage

output change in less than 4

µs—no intermediate steps are

required.

(1)

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