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HPFC-5100C Datasheet(PDF) 3 Page - Agilent(Hewlett-Packard) |
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HPFC-5100C Datasheet(HTML) 3 Page - Agilent(Hewlett-Packard) |
3 / 4 page 3 Fibre Channel Operation Fibre Channel Rate 1 Gbit/sec, 100 MBytes/sec, each direction w/full duplex support Frame Payload Size Up to 1024 bytes Topology Arbitrated Loop, Public & Private, and N_Port Fabric attachment Classes of Operation Class 3 and Class 2 (via software) Upper Layer Protocol FCP – On-chip automation for complete SCSI I/O Loop Initialization Completely hardware-based for high availability Arbitrated Loop Capabilities Loop map, loop-directed reset, loop broadcast, loop port bypass Buffer-to-Buffer Credit Four via on-chip buffers Physical Layer Interface 10-bit Interface Link Diagnostics Link status indicators, internal/external loopback, user-definable signal pins Compliance FC-PH, FC-AL, FC-AL2, FC-PLDA, FC-FLA, FCP, 10-bit profile Fibre Channel Protocol (FCP) for SCSI Features SCSI I/O Complete hardware-based management and processing of entire I/O on chip, including multiple data phases Initiator & Target Mode Yes, simultaneously Maximum # of Concurrent I/Os 32,768 I/O Request Queue Up to 8,000 commands Interrupts per I/O 1 or less Arbitration Avoidance Techniques Status and chained commands to same AL_PA sent in same loop tenancy Error Recovery Simplified error notification and recovery Addressability Byte-level addressability on all data buffers, inbound and outbound PCI Intended compliance for future Revision 2.2 DMA Channels 6 Width and Rate 32-bit or 64-bit selectable; 16 to 33 MHz. Operation to 0 MHz guaranteed by design. Burst Transfer Rate 132 or 264 Mbytes/second, guaranteed for length of frame, inbound and outbound (at 64-bit, 33 MHz) Dual Address Cycle Support Yes Voltage 3.3 V, 5 V tolerant External Sub-system ID Support Yes Additional PCI Features Zero wait state multiple cache line bursting capable up to full frame size, configurable latency timer, 32-byte cache line, Boot BIOS capable Advanced Configuration and Power Interface Yes, D0 and D3 power management states supported Tachyon TL Architectural Features Complete Hardware-Based Design Numerous independent functional blocks concurrently processing inbound data, outbound data, control and commands in hardware Six DMA channels Automation of complete I/O on-chip in hardware Results in lowest latency and I/O overhead and highest levels of parallelism Tachyon TL Specifications |
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Similar Description - HPFC-5100C |
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