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ZL10037 Datasheet(PDF) 8 Page - Zarlink Semiconductor Inc |
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ZL10037 Datasheet(HTML) 8 Page - Zarlink Semiconductor Inc |
8 / 33 page ZL10037 Data Sheet 8 Zarlink Semiconductor Inc. 2.0 Register Map and Programming The register map is arranged as 16 byte-wide read/write registers grouped by functional block. The registers may be written to and read-back from either sequentially (for lowest overhead) or specifically (for maximum flexibility). A significant number of bits are used for test and evaluation purposes only and are fixed at logic ‘0’ or ‘1’. The correct programming for these test bits is shown in the table below. It is essential that these values are programmed for correct operation. When the contents of the registers are read back the value of some bits may have changed from their programmed value. This is due to the internal automatic control which can update registers. Any changes can be ignored. Read only bits are marked with an asterisk (*). Any data written to these bits will be ignored. Registers are set to default settings on applying power. These conditions are shown below and in the applicable tables. X* denotes a read only test bit Register Block Function 0PLL PLF 214 213 212 211 210 29 28 1PLL 27 26 25 24 23 22 21 20 2 PLL 0 0 C1 C0 R3 R2 R1 R0 3 PLL X* 10 00000 4 RF Front End X* 1 1 0 1 1 LEN RFG 5 Base Band BF7 BF6 BF5 BF4 BF3 BF2 BF1 BF0 6 Base Band 0 LF SF BR4 BR3 BR2 BR1 BR0 7 Base Band BLF* BG3 BG2 BG1 BG0 0 0 0 8 Local Oscillator FLF* 01 00000 9 Local Oscillator 101 00010 A Local Oscillator 111 10001 B Local Oscillator X* X* 1 11000 C Local Oscillator 110 10000 D Local Oscillator X* X* X* 10000 E Local Oscillator X* X* 1 10000 F General PD CLR P0 0 ZI3* ZI2* ZI1* ZI0* Table 2 - Register Map |
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