10

MC68307 TECHNICAL INFORMATION

MOTOROLA

External Bus Interface

The external bus interface handles the transfer of information between the internal EC000 core and the memory,

peripherals, or other processing elements in the external address space. It consists of a 68000 bus interface and

an 8051-compatible bus interface. The external 68000 bus provides up to 24 address lines and 16 data lines.

Each bus access can appear externally either as a 68000 bus cycle (either 16-bit or 8-bit dynamic data bus width)

or as an 8-bit wide 8051-compatible bus cycle (multiplexing 8 bits of address and data) with the appropriate sets

of control signals.

Parallel General-Purpose I/O Ports

The MC68307 supports two general-purpose I/O ports, port A (8-bits) and port B (16-bits), whose pins can be

configured as general-purpose I/O pins or as dedicated peripheral interface pins for the on-chip modules.

Each port pin can be independently programmed as general-purpose I/O pins, even when other pins related to

the same on-chip peripheral are used as dedicated pins. Even if all the pins for a particular peripheral are

configured as general-purpose I/O, the peripheral will still operate normally (although this is only useful in the

case of the timer module). Power consumption may be reduced by turning off unused modules.

Interrupt Controller

The interrupt controller supports interrupts from three sources. The first source is an external, nonmaskable

interrupt input on the IRQ7 signal, which always causes an interrupt priority level 7 request to the EC000 core.

Assuming no other source is programmed as a level 7 source, this input will always obtain the immediate

attention of the core.

The second source is an external interrupt received through the 8-channel latched interrupt port (INT8–INT1).

Each INTx signal can be programmed with an interrupt priority level, and each can have pending interrupts

cleared independently of the others.

The third source of interrupts is the on-chip peripherals. The interrupt controller allows the user to assign the

interrupt priority level each of the four on-chip peripherals will use, and to determine a particular vector number

to be presented when the respective module receives an interrupt acknowledge from the processor via the

interrupt controller logic.

Software Watchdog

A software watchdog timer is used to protect against system failures by providing a means to escape from

unexpected input conditions, external events, or programming errors. Once started, the software watchdog timer

must be cleared by software on a regular basis so that it never reaches its time-out value. Upon reaching the

time-out value, the assumption is made that a system failure has occurred, and the software watchdog logic

resets the MC68307.