TM124MBK36B, TM124MBK36R 1048576 BY 36-BIT

TM248NBK36B, TM248NBK36R 2097152 BY 36-BIT

DYNAMIC RAM MODULE

SMMS137E – JANUARY 1991 – REVISEDJUNE 1995

9

POST OFFICE BOX 1443

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature

PARAMETER

’124MBK36B-60

’248NBK36B-60

’124MBK36B-70

’248NBK36B-70

’124MBK36B-80

’248NBK36B-80

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tCAC

Access time from CAS low

15

18

20

ns

tAA

Access time from column address

30

35

40

ns

tRAC

Access time from RAS low

60

70

80

ns

tCPA

Access time from column precharge

35

40

45

ns

tCLZ

CAS to output in low impedance

0

0

0

ns

tOFF

Output disable time after CAS high (see Note 6)

0

15

0

18

0

20

ns

NOTE 6: tOFF is specified when the output is no longer driven.

timing requirements over recommended ranges of supply voltage and operating free-air

temperature

’124MBK36B-60

’248NBK36B-60

’124MBK36B-70

’248NBK36B-70

’124MBK36B-80

’248NBK36B-80

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tRC

Cycle time, random read or write (see Note 7)

110

130

150

ns

tRWC

Cycle time, read write

130

153

175

ns

tPC

Cycle time, page-mode read or write (see Note 8)

40

45

50

ns

tRASP

Pulse duration, page mode, RAS low

60

100 000

70

100 000

80

100 000

ns

tRAS

Pulse duration, nonpage mode, RAS low

60

10 000

70

10 000

80

10 000

ns

tCAS

Pulse duration, CAS low

15

10 000

18

10 000

20

10 000

ns

tCP

Pulse duration, CAS high

10

10

10

ns

tRP

Pulse duration, RAS high (precharge)

40

50

60

ns

tWP

Pulse duration, write

15

15

15

ns

tASC

Setup time, column address before CAS low

0

0

0

ns

tASR

Setup time, row address before RAS low

0

0

0

ns

tDS

Setup time, data

0

0

0

ns

tRCS

Setup time, read before CAS low

0

0

0

ns

tCWL

Setup time, W low before CAS high

15

18

20

ns

tRWL

Setup time, W low before RAS high

15

18

20

ns

tWCS

Setup time, W low before CAS low

0

0

0

ns

tWSR

Setup time, W high (see Note 9)

10

10

10

ns

NOTES:

7. All cycles assume tT = 5 ns.

8. To assure tPC min, tASC should be ≥ 5 ns.

9. CBR refresh only