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ICL8052CPD Datasheet(PDF) 11 Page - Intersil Corporation |
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ICL8052CPD Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 19 page 3-44 ICL8052 vs ICL8068 The ICL8052 offers significantly lower input leakage currents than the ICL8068, and may be found preferable in systems with high input impedances. However, the ICL8068 has substantially lower noise voltage, and is the device of choice for systems where noise is a limiting factor, particularly in low signal level conditions. Max Clock Frequency The maximum conversion rate of most dual-slope A/D converters is limited by frequency response of the compara- tor. The comparator in this circuit is no exception, even though it is entirely NPN with an open-loop, gain-bandwidth product of 300MHz. The comparator output follows the inte- grator ramp with a 3 µs delay, and at a clock frequency of 160kHz (6 µs period) half of the first reference integrate clock period is lost in delay. This means that the meter reading will change from 0 to 1 with 50 µV input, 1 to 2 with 150µV, 2 to 3 at 250 µV, etc. This transition at midpoint is considered desirable by most users. However, if the clock frequency is increased appreciably above 160kHz, the instrument will flash “1” on noise peaks even when the input is shorted. For many dedicated applications where the input signal is always on one polarity, the dealy of the comparator need not be limitation. Since the non-linearity and noise do not increase substantially with frequency, clock rates of up to approximately 1MHz may be used. For a fixed clock frequency, the extra count or counts caused by comparator delay will be a constant and can be subtracted out digitally. The minimum clock frequency is established by leakage on the auto-zero and reference caps. With most devices, measurement cycles as long as 10 seconds give no measur- able leakage error. To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 300kHz, 200kHz, 150kHz, 120kHz, 100kHz, 40kHz, 331/3kHz, etc, should be selected. For 50Hz rejection, oscillator frequencies of 250kHz, 1662/3kHz, 125kHz, 100kHz, etc. would be suitable. Note that 100kHz (2.5 readings/second) will reject both 50Hz and 60Hz. The clock used should be free from significant phase or frequency jitter. A simple two-gate oscillator and one based on CMOS 7555 timer are shown in the Applications section. The multiplexed output means that if the display takes significant current from the logic supply, the clock should have good PSRR. Applications Specific Circuits Using the 8068/71C03 8052/71C03 Figure 7 shows the complete circuit for a ±41/2 digit ( ±200mV full scale) A/D converter with LED readout using the internal reference of the 8068/52. If an external reference is used, the reference supply (pin 7) should be connected to ground and the 300pF reference cap deleted. The circuit also shows a typical RC input filter. Depending on the application, the time-constant of this filter can be made faster, slower, or the filter deleted completely. The 1/2 digit LED is driven from the 7-segment decoder, with a zero reading blanked by connecting a D5 signal to RBI input of the decoder. A voltage translation network is connected between the com- parator output of the 8068/52 and the auto-zero input of the 71C03. The purpose of this network is to assure that, during auto-zero, the output of the comparator is at or near the threshold of the 71C03 logic (+2.5V) while the auto-zero capacitor is being charged to VREF (+100mV for a 200mV instrument). Otherwise, even with 0V in, some reference inte- grate period would be required to drive the comparator output to the threshold level. This would show up as an equivalent offset error. Once the divider network has been selected, the unit-to-unit variation should contribute less than a tenth of a count error. A second feature is the back-to-back diodes, used to lower the noise. In the normal operating mode they offer a high impedance and long integrating time constant to any noise pulses charging the auto-zero cap. At startup or recov- ery from an overload, their impedance is low to large signals so that the cap can be charged up in one auto-zero cycle. The buffer gain does not have to be set precisely at 10 since the gain is used in both the integrate and deintegrate phase. For scale factors other then 200mV the gain of the buffer should be changed to give a ±2V buffer output. For 2.0000V full scale this means unity gain and for 20,000mV (1 µV resolution) a gain of 100 is necessary. Not all 8068As can operate properly at a gain of 100 since their offset should be less than 10mV in order to accommodate the auto-zero circuitry. However, for devices selected with less than 10mV offset, the noise perfor- mance is reasonable with approximately 1.5 µV near full scale. On all scales less than 200mV, the voltage translation network should be made adjustable as an offset trim. The auto-zero cap should be 1 µF for all scales and the refer- ence capacitor should be 1 µF times the gain of the buffer amplifier. At this value if the input leakages of the 8052/8068 are equal, the droop effects will cancel giving zero offset. This is especially important at high temperature. Some typical component values are shown in Table 1. For 31/2 digit conversion, use 12kHz clock. V++ = +15V, V+ = 5V, V- = -15V Clock Freq. = 120kHz (41/2 Digit) or 12kHz (3 1/ 2 Digit) TABLE 1. SPECIFICATION VALVE UNITS Full Scale VIN 20 200 2000 mV Buffer Gain 100 (See Note) 10 1 V/V RINT 100 100 100 k Ω CINT 0.22 0.22 0.22 µF CAZ 1.0 1.0 1.0 µF CREF 10 10 1.0 µF VREF 10 100 1000 mV Resolution (41/2 Digit) 1 10 100 µV NOTE: Comment on offset limitations above. Buffer gain does not improve ICL8052 noise performance adequately. RB1 RB2 + () RB2 ------------------------------------ ICL8052/ICL71C03, ICL8068/ICL71C03 |
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