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AT89S2051-24SC Datasheet(PDF) 9 Page - ATMEL Corporation |
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AT89S2051-24SC Datasheet(HTML) 9 Page - ATMEL Corporation |
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9 / 45 page  9 3390C–MICRO–7/05 AT89S2051/S4051 10.2 Brown-out Reset The AT89S2051/S4051 has an on-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD is nominally 2.2V. The purpose of the BOD is to ensure that if V CC fails or dips while executing at speed, the system will gracefully enter reset without the possibility of errors induced by incorrect execution. When V CC decreases to a value below the trigger level, the Brown-out Reset is imme- diately activated. When V CC increases above the trigger level, the BOD delay counter starts the microcontroller after the timeout period has expired in approximately 2 ms. 10.3 External Reset The RST pin functions as an active-high reset input. The pin must be held high for at least two machine cycles to trigger the internal reset. RST also serves as the In-System Programming (ISP) enable input. ISP mode is enabled when the external reset pin is held high and the ISP Enable fuse is set. 11. Clock Register . Table 11-1. CLKREG – Clock Register CLKREG = 8FH Reset Value = XXXX XX0XB Not Bit Addressable – ––––– PWDEX X2 Bit 7 65432 10 Symbol Function PWDEX Power-down Exit Mode. When PWDEX = 1, wake up from Power-down is externally controlled. When PWDEX = 0, wake up from Power-down is internally timed. X2 When X2 = 0, the frequency (at XTAL1 pin) is internally divided by 2 before it is used as the device system frequency. When X2 = 1, the divide by 2 is no longer used and the XTAL1 frequency becomes the device system frequency. This enables the user to use a 6 MHz crystal instead of a 12 MHz crystal in order to reduce EMI. The X2 bit is initialized on power-up with the value of the X2 user fuse and may be changed at runtime by software. |
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