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DM54S194N16E Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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DM54S194N16E Datasheet(HTML) 1 Page - National Semiconductor (TI) |
1 / 6 page TLF6475 June 1989 DM54S194DM74S194 4-Bit Bidirectional Universal Shift Registers General Description These bidirectional shift registers are designed to incorpo- rate virtually all of the features a system designer may want in a shift register they feature parallel inputs parallel out- puts right-shift and left-shift serial inputs operating-mode- control inputs and a direct overriding clear line The register has four distinct modes of operation namely Parallel (broadside) load Shift right (in the direction QA toward QD) Shift left (in the direction QD toward QA) Inhibit clock (do nothing) Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs S0 and S1 high The data are loaded into the associated flip- flops and appear at the outputs after the positive transition of the clock input During loading serial data flow is inhibit- ed Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low Serial data for this mode is entered at the shift-right data input When S0 is low and S1 is high data shifts left syn- chronously and new data is entered at the shift-left serial input Clocking of the flip-flop is inhibited when both mode control inputs are low Features Y Parallel inputs and outputs Y Four operating modes Synchronous parallel load Right shift Left shift Do nothing Y Positive edge-triggered clocking Y Direct overriding clear Y Typical clock frequency 105 MHz Y Typical power dissipation 425 mW Connection Diagram Dual-In-Line Package TLF6475 – 1 Order Number DM54S194J or DM74S194N See NS Package Number J16A or N16E C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
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