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ADSP-21262SKBCZ200 Datasheet(PDF) 3 Page - Analog Devices |
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ADSP-21262SKBCZ200 Datasheet(HTML) 3 Page - Analog Devices |
3 / 44 page ADSP-21262 Rev. A | Page 3 of 44 | May 2004 TABLE OF CONTENTS General Description ..................................................4 ADSP-21262 Family Core Architecture .......................4 SIMD Computational Engine ................................4 Independent, Parallel Computation Units .................5 Data Register File ................................................5 Single-Cycle Fetch of Instruction and Four Operands ..5 Instruction Cache ...............................................5 Data Address Generators With Zero-Overhead Hardware Circular Buffer Support .......................5 Flexible Instruction Set ........................................6 ADSP-21262 Memory and I/O Interface Features ..........6 Dual-Ported On-Chip Memory ..............................6 DMA Controller .................................................6 Digital Audio Interface (DAI) ................................6 Serial Ports ........................................................6 Serial Peripheral (Compatible) Interface ...................8 Parallel Port ......................................................8 Timers .............................................................8 ROM Based Security ............................................8 Program Booting ................................................8 Phase-Locked Loop ............................................8 Power Supplies ...................................................8 Target Board JTAG Emulator Connector .....................9 Development Tools ................................................9 Designing an Emulator-Compatible DSP Board (Target) ................................................. 10 Additional Information ......................................... 10 Pin Function Descriptions ........................................ 11 Address Data Pins as FLAGs .................................. 14 Boot Modes ........................................................ 14 Core Instruction Rate to CLKIN Ratio Modes ............. 14 Address Data Modes ............................................. 14 ADSP-21262 Specifications ....................................... 15 Recommended Operating Conditions ....................... 15 Electrical Characteristics ........................................ 15 Absolute Maximum Ratings ................................... 16 ESD Sensitivity .................................................... 16 Timing Specifications ........................................... 16 Power-up Sequencing ........................................ 18 Clock Input ..................................................... 19 Clock Signals ................................................... 19 Reset ............................................................. 20 Interrupts ........................................................20 Core Timer ......................................................20 Timer PWM_OUT Cycle Timing ..........................21 Timer WDTH_CAP Timing ................................21 DAI Pin to Pin Direct Routing .............................22 Precision Clock Generator (Direct Pin Routing) .......23 Flags ..............................................................24 Memory Read–Parallel Port .................................25 Memory Write—Parallel Port ..............................27 Serial Ports ......................................................29 Input Data Port (IDP) ........................................32 Parallel Data Acquisition Port (PDAP) ...................33 SPI Interface—Master ........................................34 SPI Interface—Slave ...........................................35 JTAG Test Access Port and Emulation ...................36 Output Drive Currents ..........................................37 Test Conditions ...................................................37 Capacitive Loading ...............................................37 Environmental Conditions .....................................38 Thermal Characteristics .........................................38 136-Ball BGA Pin Configurations ................................39 144-LQFP Pin Configurations ....................................42 Package Dimensions ................................................ 43 Ordering Guide ......................................................44 REVISION HISTORY 4/04–Data Sheet Changed from Rev. 0 to Rev. A Added notes to AD pins ............................................11 Added VIHCLKIN and VILCLKIN specifications .....................15 Changed specifications (tALERW, and tALEHZ) ................25-28 Updated 136-BGA package drawing ............................43 |
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