FLASH MEMORY

9

K9F6408U0C

PRODUCT INTRODUCTION

The K9F6408U0C is a 66Mbit(69,206,016 bit) memory organized as 16,384 rows(pages) by 528 columns. Spare sixteen columns are

located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data trans-

fer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells

that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND

structured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is shown

in Figure 2. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis.

The memory array consists of 1024 separately erasable 8K-byte blocks. It indicates that the bit by bit erase operation is prohibited on

the K9F6408U0C.

The K9F6408U0C has addresses multiplexed into 8 I/O

′s. This scheme dramatically reduces pin counts and allows systems

upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through

I/O

′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address

Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle

except for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block

address loading. The 8M byte physical space requires 23 addresses, thereby requiring three cycles for byte-level addressing: column

address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles

following the required command input. In Block Erase operation, however, only the two row address cycles are used.

Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of

the K9F6408U0C.

Table 1. COMMAND SETS

NOTE : 1. The 00h command defines starting address of the 1st half of registers.

The 01h command defines starting address of the 2nd half of registers.

After data access on the 2nd half of register by the 01h command, the status pointer is

automatically moved to the 1st half register(00h) on the next cycle.

2. The 50h command is valid only when the GND input(pin #40) is low level.

Function

1st. Cycle

2nd. Cycle

Acceptable Command during Busy

Read 1

-

Read 2

-

Read ID

90h

-

Reset

FFh

-

O

Page Program

80h

10h

Block Erase

60h

D0h

Read Status

70h

-

O

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.