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L6710 Datasheet(PDF) 8 Page - STMicroelectronics |
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L6710 Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 34 page L6710 8/34 REFERENCE SCHEMATIC DEVICE DESCRIPTION The device is an integrated circuit realized in BCD technology. It provides complete control logic and pro- tections for a high performance dual-phase step-down DC-DC converter optimized for microprocessor power supply. It is designed to drive N Channel MOSFETs in a two-phase synchronous-rectified buck to- pology. A 180 deg phase shift is provided between the two phases allowing reduction in the input capacitor current ripple, reducing also the size and the losses. The output voltage of the converter can be precisely regulated, programming the VID pins, from 0.8375 to 1.6000V with 12.5mV binary steps, with a maximum tolerance on the output regulated voltage of ±0.5% over temperature and line voltage variations. Since the VID pins program the maximum output voltage, the device automatically regulates to a voltage VID*=VID-25mV avoiding use of any external component to lower the regulated voltage. Dynamic VID Code changes are managed stepping to the new configura- tion following the VID table with no need for external components. The device provides an average cur- rent-mode control with fast transient response. It includes a 150kHz oscillator externally adjustable through a resistor. The error amplifier features a 15V/ µs slew rate that permits high converter bandwidth for fast transient performances. Current information is read across the lower mosfets RdsON or across a sense resistor placed in series to the LS mos in fully differential mode. The current information corrects the PWM output in order to equalize the average current carried by each phase. Current sharing between the two phases is then limited at ±10% over static and dynamic conditions unless considering the sensing element spread. The device protects against Over-Current, with an OC threshold for each phase, entering in constant cur- rent mode. Since the current is read across the low side mosfets, the device keeps constant the bottom of the inductors current triangular waveform. When an under voltage is detected the device latches and the FAULT pin is driven high. The device performs also Over-Voltage protection that disables immediately the device turning ON the lower driver and driving high the FAULT pin. L6710 PGOOD PGND PGNDS ISEN2 LGATE2 VSEN FB PHASE2 HGATE2 BOOT2 VCC COMP SGND REF_OUT VID0 VID1 VID2 VID3 VID4 To PGNDS ISEN1 LGATE1 PHASE1 HGATE1 BOOT1 VCCDR 5 31 35 36 38 21 20 41 3 43 42 40 19 28 27 26 24 25 6, 7 39 30 13 9 8 14 18 OUTEN FBG 12 RFB RF CF Rg Rg LS2 HS2 L2 CIN COUT S1 S0 S3 S2 S4 Rg LS1 L1 HS1 Vin GNDin PGOOD CPU Rg VID5 29 S5 OSC / FAULT 22 17 FBR VID_Pgood To VCC |
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