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ADS1207 Datasheet(PDF) 5 Page - Burr-Brown (TI) |
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ADS1207 Datasheet(HTML) 5 Page - Burr-Brown (TI) |
5 / 8 page ADS1206 ADS1207 SBAS311 − MARCH 2004 www.ti.com 5 PIN ASSIGNMENTS VSSOP PACKAGE (TOP VIEW) 1 2 3 4 8 7 6 5 BUF FOUT V DD VIN CLKOUT CLKIN GND REFIN/OUT Terminal Functions TERMINAL NAME NO. DESCRIPTION CLKOUT 1 Clock output CLKIN 2 Master clock input GND 3 Ground REFIN/OUT 4 Reference voltage input or output VIN 5 Analog input VDD 6 Power supply, +3.3V or +5V nominal FOUT 7 Modulator output BUF 8 Buffered mode select PARAMETER MEASUREMENT INFORMATION CLKIN t C1 t W2 t W1 t D1 t R1 t F1 FOUT Figure 1. Timing Diagram TIMING REQUIREMENTS: 5.0V over recommended operating free-air temperature range at −40 °C to +85°C,, and VDD = 5V, unless otherwise noted. PARAMETER MIN MAX UNITS tC1 Input clock period ADS1206 1000 TBD ns tC1 Input clock period ADS1207 250 TBD ns tW1 Input clock high time (tC1/2) − 100 (tC1/2) + 100 ns tD1 FOUT rising edge delay after input clock rising edge TBD TBD ns tW2 FOUT high time tC1 − 20 tC1 + 20 ns tR1 FOUT rise time TBD TBD ns tF1 FOUT fall time TBD TBD ns NOTE: Applicable for 5.0V nominal supply: VDD (min) = 4.5V and VDD (max) = 5.5V. All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagram. TIMING REQUIREMENTS: 3.3V over recommended operating free-air temperature range at −40 °C to +85°C,, and VDD = 3.3V, unless otherwise noted. PARAMETER MIN MAX UNITS tC1 Input clock period ADS1206 1000 TBD ns tC1 Input clock period ADS1207 250 TBD ns tW1 Input clock high time (tC1/2) − 100 (tC1/2) + 100 ns tD1 FOUT rising edge delay after input clock rising edge TBD TBD ns tW2 FOUT high time tC1 − 8 tC1 + 8 ns tR1 FOUT rise time TBD TBD ns tF1 FOUT fall time TBD TBD ns NOTE: Applicable for 3.3V nominal supply: VDD (min) = 3.0V and VDD (max) = 3.6V. All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagram. |
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