CY7B951
3
Description
The CY7B951 Local Area Network ATM Transceiver is used in
SONET/SDH and ATM applications to recover clock and data
information from a 155.52-MHz or 51.84-MHz NRZ (Non Re-
turn to Zero) or NRZI (Non Return to Zero Invert on ones)
serial data stream. This device also provides a bit-rate Trans-
mit clock, from a byte rate source through the use of a frequen-
cy multiplier PLL, and differential data buffering for the Trans-
mit side of the system (see
Figure 1).
Operating Frequency
The CY7B951 operates at either of two frequency ranges. The
MODE input selects which of the two frequency ranges the
Transmit frequency multiplier PLL and the Receive clock and
data recovery PLL will operate. The MODE input has three
different functional selections. When MODE is connected to
VCC, the highest operating range of the device is selected. A
19.44-MHz
±1% source must drive the REFCLK input and the
two PLLs will multiply this rate by 8 to provide output clocks
that operate at 155.52 MHz
±1%. When the MODE input is
connected to ground (GND), the lowest operating range of the
device is selected. A 6.48-MHz
±1% source must drive the
REFCLK inputs and the two PLLs will multiply this rate by 8 to
provide output clocks that operate at 51.84 MHz
±1%. When
the MODE input is left unconnected or forced to approximately
VCC/2, the device enters Test mode.
Transmit Functions
The transmit section of the CY7B951 contains a PLL that takes
a REFCLK input and multiplies it by 8 (REFCLK
×8) to produce
a PECL (Pseudo ECL) differential output clock (TCLK
±). The
transmitter has two operating ranges that are selectable with
the three-level MODE pin as explained above. The CY7B951
Transmit frequency multiplier PLL allows low-cost byte rate
clock sources to be used to time the upstream serial data
transmitter as shown in
Figure 1.
The REFCLK
± input can be configured three ways. When both
REFCLK+ and REFCLK- are connected to a differential
100K-compatible PECL source, the REFCLK input will behave
as a differential PECL input. When either the REFCLK- or the
REFCLK+ input is at a TTL LOW, the other REFCLK input
becomes a TTL-level input allowing it to be connected to a
low-cost TTL crystal oscillator. The REFCLK input structure,
therefore, can be used as a differential PECL input, a single
TTL input, or as a dual TTL clock multiplexing input.
The Transmit PECL differential input pair (TSER
±) is buffered
by the CY7B951 yielding the differential data outputs (TOUT
±).
These outputs can be used to directly drive transmission me-
dia such as Printed Circuit Board (PCB) traces, optical drivers,
twisted pair, or coaxial cable.
Receive Functions
The primary function of the receiver is to recover clock
(RCLK
±) and data (RSER±) from the incoming differential
PECL data stream (RIN
±) without the need for external buffer-
ing. These built-in line receiver inputs, as well as the TSER
±
inputs mentioned above, have a wide common-mode range
(2.5V) and the ability to receive signals with as little as 50 mV
differential voltage. They are compatible with all PECL signals
and any copper media.
The clock recovery function is performed using an embedded
PLL. The recovered clock is not only passed to the RCLK
±
outputs, but also used internally to sample the input serial
stream in order to recover the data pattern. The Receive PLL
uses the REFCLK input as a byte-rate reference. This input is
multiplied by 8 (REFCLK
×8) and is used to improve PLL lock
time and to provide a center frequency for operation in the
absence of input data stream transitions. The receiver can re-
cover clock and data in two different frequency ranges depend-
ing on the state of the three-level MODE pin as explained ear-
lier. To insure accurate data and clock recovery, REFCLK
×8
must be within 1000 ppm of the transmit bit rate. The stan-
dards, however, specify that the REFCLK
×8 frequency accu-
racy be within 20
−100 ppm.
The differential input serial data (RIN
±) is not only used by the
PLL to recover the clock and data, but it is also buffered and
presented as the PECL differential output pair ROUT
±. This
output pair can be used as part of the transmission line inter-
face circuit for base line wander compensation, improving sys-
tem performance by providing reduced input jitter and in-
creased data eye opening.
Carrier Detect (CD) and Link Fault Indicator (LFI) Func-
tions
The Link Fault Indicator (LFI) output is a TTL-level output that
indicates the status of the receiver. This output can be used by
an external controller for Loss of Signal (LOS), Loss of Frame
(LOF), or Out of Frame (OOF) indications. LFI is controlled by
the Carrier Detect input, the internal Transitions Detector, and
the PLL Out of Lock (OOL) circuitry.
MODE
3-Level In
Frequency Mode Select. This three-level input selects the frequency range for the clock and data
recovery Receive PLL and the frequency multiplier Transmit PLL. When this input is held HIGH the
two PLLs operate at the SONET (SDH) STS-3 (STM-1) line rate of 155.52 MHz. When this input is
held LOW the two PLLs operate at the SONET STS-1 line rate of 51.84 MHz. The REFCLK
±
frequency in both operating modes is 1/8 the PLL operating frequency. When the MODE input is left
floating or held at VCC/2 the TSER± inputs substitute for the internal PLL VCO for use in factory
testing.
VCC
Power.
VSS
Ground.
Pin Descriptions (continued)
Name
I/O
Description
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