EM785840/5841/5842

8-bit Micro-controller

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* This specification is subject to change without notice.

8

2004/11/10

V1.2

"MOV R2, A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are

cleared to "0''.

"ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are

cleared to "0''.

"TBL" allows a relative address added to the current PC, and contents of the ninth and tenth bits don't change.

The most significant bit (A10~A11) will be loaded with the contents of bit PS0~PS1 in the status register (R5

PAGE0) upon the execution of a "JMP'', "CALL'', "ADD R2, A'', or "MOV R2, A'' instruction.

If an interrupt is triggered, PROGRAM ROM will jump to address 0x08 at page0. The CPU will store ACC,

R3 status and R5 PAGE automatically, and they will be restored after instruction RETI.

A11 A10

A9 A8

A7~A0

0 0

PAGE0 00000~003FF

0 1

PAGE1 00400~007FF

1 0

PAGE2 00800~00BFF

STACK1

STACK2

STACK5

STACK4

STACK3

STACK6

STACK8

STACK7

CALL

and

INTERRUPT

RET

RETL

RETI

ACC,R3,R5(PAGE)

R5(PAGE)

store

restore

1 1

PAGE3 00C00~00FFF

Fig.3 Program counter organization

R3 (Status, Page selection)

(Status flag, Page selection bits)

7

6

5

4

3

2

1

0

RPAGE1

RPAGE0

IOCPAGE

T

P

Z

DC

C

R/W-0

R/W-0

R/W-0

R

R

R/W

R/W

R/W

Bit 0(C) : Carry flag

Bit 1(DC) : Auxiliary carry flag

Bit 2(Z) : Zero flag

Bit 3(P) : Power down bit

Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command.

Bit 4(T) : Time-out bit

Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout.

EVENT

T

P

REMARK

WDT wake up from sleep mode

0

0

WDT time out (not sleep mode)

0

1

/RESET wake up from sleep

1

0

Power up

1

1

Low pulse on /RESET

x

X

x : don't care

Bit 5(IOCPAGE) : change IOC5 ~ IOCE to another page

Please refer to Fig.4 control register configuration for details.

0/1

IOC page0 / IOC page1