©2005 Fairchild Semiconductor Corporation

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FQD3N50C/FQU3N50C Rev. A

FQD3N50C/FQU3N50C

500V N-Channel MOSFET

Features

• Low gate charge ( typical 10 nC )

• Low Crss ( typical 8.5 pF)

• Fast switching

• 100 % avalanche tested

• Improved dv/dt capability

Description

These N-Channel enhancement mode power field effect transis-

tors are produced using Fairchild’s proprietary, planar stripe,

DMOS technology.

This advanced technology has been especially tailored to mini-

mize on-state resistance, provide superior switching perfor-

mance, and withstand high energy pulse in the avalanche and

commutation mode. These devices are well suited for high effi-

ciency switched mode power supplies, active power factor cor-

rection, electronic lamp ballasts based on half bridge topology.

Absolute Maximum Ratings

Thermal Characteristics

* When mounted on the minimum pad size recommended (PCB Mount)

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S

D

G

I-PAK

FQU Series

D-PAK

FQD Series

GS

D

GS

D

Symbol

Parameter

FQD3N50C/FQU3N50C

Units

Drain-Source Voltage

500

V

Drain Current

2.5

A

1.5

A

Drain Current

- Pulsed

(Note 1)

10

A

Gate-Source Voltage

± 30

V

Single Pulsed Avalanche Energy

(Note 2)

200

mJ

Avalanche Current

(Note 1)

2.5

A

Repetitive Avalanche Energy

(Note 1)

3.5

mJ

dv/dt

Peak Diode Recovery dv/dt

(Note 3)

4.5

V/ns

35

W

- Derate above 25°C

0.28

W/°C

Operating and Storage Temperature Range

-55 to +150

°C

Maximum lead temperature for soldering purposes,

1/8" from case for 5 seconds

300

°C

Symbol

Parameter

Typ

Max

Units

Thermal Resistance, Junction-to-Case

--

3.5

°C/W

Thermal Resistance, Junction-to-Ambient*

--

50

°C/W

Thermal Resistance, Junction-to-Ambient

--

110

°C/W