6.42

IDT70V9289L

High-Speed 64K x 16 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

8

Timing Waveform of Read Cycle for Flow-Through Output

Timing Waveform of Read Cycle for Pipelined Operation

An

An + 1

An + 2

An + 3

ADDRESS

CLK

OE

Qn

Qn + 1

Qn + 2

4855 drw 06

(1)

(1)

(1)

(1)

(2)

UB, LB

(4)

(5)

An

An + 1

An + 2

An + 3

ADDRESS

CLK

UB, LB

(4)

OE

Qn

Qn + 1

Qn + 2

4855 drw 07

(1)

(1)

(1)

(2)

(5)

(1 Latency)

(6)

(6)

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2.

OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.

3.

4. The output is disabled (High-Impedance state) by

are for reference use only.

6. If

7. "X' here denotes Left or Right port. The diagram is with respect to that port.