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MSM7704 Datasheet(PDF) 6 Page - OKI electronic componets |
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MSM7704 Datasheet(HTML) 6 Page - OKI electronic componets |
6 / 17 page ¡ Semiconductor MSM7704-01/02/03 6/17 XSYNC Transmit synchronizing signal input. PCM output signal from the DOUT1 and DOUT2 pins is output in synchronization with this transmit synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. This synchronizing signal must be synchronized in phase with BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the transmit section. However, unless the frequency characteristics of the system used are strictly specified, this device can operate in the range of 6 kHz to 9 kHz, but the electrical characteristics are not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to power saving state. DOUT1 PCM signal output of channel 1 when the parallel mode is selected. The PCM output signal is output from MSD in a sequential order, synchronizing with the rising edge of the BCLK signal. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power-saving state or power-down state. When the serial mode is selected, this pin is configured to be the output of serial multiplexed 2ch PCM signal. A pull-up resistor must be connected to this pin because it is an open drain output. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7704-03 (A-law) outputs the character signal, inverting the even bits. Input/Output Level +Full scale +0 –0 –Full scale PCMIN/PCMOUT MSM7704-02 ( m-law) MSD 1000 0000 1111 1111 0111 1111 0000 0000 MSM7704-03 (A-law) MSD 1010 1010 1101 0101 0101 0101 0010 1010 |
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