CY7C1327F
Document #: 38-05216 Rev. *B
Page 7 of 17
Truth Table[ 2, 3, 4, 5, 6]
Next Cycle
Add. Used
ZZ
CE1
CE2
CE3
ADSP
ADSC
ADV
OE
DQ
WRITE
Unselected
None
L
H
X
X
X
L
X
X
three-state X
Unselected
None
L
L
X
H
L
X
X
X
three-state X
Unselected
None
L
L
L
X
L
X
X
X
three-state X
Unselected
None
L
L
X
H
H
L
X
X
three-state X
Unselected
None
L
L
L
X
H
L
X
X
three-state X
Begin Read
External
L
L
H
L
L
X
X
X
three-state X
Begin Read
External
L
L
H
L
H
L
X
X
three-state Read
Continue Read Next
L
X
X
X
H
H
L
H
three-state Read
Continue Read Next
L
X
X
X
H
H
L
L
DQ
Read
Continue Read Next
L
H
X
X
X
H
L
H
three-state Read
Continue Read Next
L
H
X
X
X
H
L
L
DQ
Read
Suspend Read Current
L
X
X
X
H
H
H
H
three-state Read
Suspend Read Current
L
X
X
X
H
H
H
L
DQ
Read
Suspend Read Current
L
H
X
X
X
H
H
H
three-state Read
Suspend Read Current
L
H
X
X
X
H
H
L
DQ
Read
Begin Write
Current
L
X
X
X
H
H
H
X
three-state Write
Begin Write
Current
L
H
X
X
X
H
H
X
three-state Write
Begin Write
External
L
L
H
L
H
H
X
X
three-state Write
Continue Write Next
L
X
X
X
H
H
H
X
three-state Write
Continue Write Next
L
H
X
X
X
H
H
X
three-state Write
Suspend Write Current
L
X
X
X
H
H
H
X
three-state Write
Suspend Write Current
L
H
X
X
X
H
H
X
three-state Write
ZZ “Sleep”
None
H
X
X
X
X
X
X
X
three-state X
Truth Table for Read/Write[2]
Function
GW
BWE
BWB
BWA
Read
H
H
X
X
Read
H
L
H
H
Write Byte A – (DQA and DQPA)H
L
H
L
Write Byte B – (DQB and DQPB)H
L
L
H
Write Bytes B, A
H
L
L
L
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BWA, BWB),
BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: B]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
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