11 / 17 page
CY7C1327F
Document #: 38-05216 Rev. *B
Page 11 of 17
Switching Waveforms
Read Cycle Timing[16]
Notes:
16. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
17. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW.
tCYC
t
CL
CLK
ADSP
t
ADH
t
ADS
ADDRESS
t
CH
OE
ADSC
CE
tAH
tAS
A1
tCEH
tCES
GW, BWE,
BW[A:B]
Data Out (Q)
High-Z
tCLZ
tDOH
tCO
ADV
tOEHZ
tCO
Single READ
BURST READ
tOEV
tOELZ
tCHZ
ADV
suspends
burst.
Burst wraps around
to its initial state
tADVH
tADVS
tWEH
tWES
tADH
tADS
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Q(A2)
Q(A2 + 1)
Q(A2 + 3)
A2
A3
Deselect
cycle
Burst continued with
new base address
DON’T CARE
UNDEFINED
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