PRELIMINARY
CY7C1352G
Document #: 38-05514 Rev. *A
Page 7 of 13
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... −65°C to +150°C
Ambient Temperature with
Power Applied
.................................................. −55°C to +125°C
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
DC Voltage Applied to Outputs
in tri-state
..................................................−0.5V to V
DDQ + 0.5V
DC Input Voltage
...................................... −0.5V to V
DD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Ambient
Temperature (TA)VDD
VDDQ
Com’l
0°C to +70°C
3.3V – 5%/+10%
2.5V –5%
to VDD
Ind’l
–40°C to +85°C
Electrical Characteristics Over the Operating Range [9, 10]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VDD
Power Supply Voltage
3.135
3.6
V
VDDQ
I/O Supply Voltage
2.375
VDD
V
VOH
Output HIGH Voltage
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
2.4
V
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
2.0
V
VOL
Output LOW Voltage
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
0.4
V
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
0.4
V
VIH
Input HIGH Voltage[9]
VDDQ = 3.3V
2.0
VDD + 0.3V
V
VDDQ = 2.5V
1.7
VDD + 0.3V
V
VIL
Input LOW Voltage[9]
VDDQ = 3.3V
–0.3
0.8
V
VDDQ = 2.5V
–0.3
0.7
V
IX
Input Load Current except ZZ
and MODE
GND
≤ V
I ≤ VDDQ
−55
µA
Input Current of MODE
Input = VSS
−30
µA
Input = VDD
5
µA
Input Current of ZZ
Input = VSS
−5
µA
Input = VDD
30
µA
IOZ
Output Leakage Current
GND
≤ V
I ≤ VDDQ, Output Disabled
−55
µA
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
4-ns cycle, 250 MHz
325
mA
5-ns cycle, 200 MHz
265
mA
6-ns cycle, 166 MHz
240
mA
7.5-ns cycle, 133
MHz
225
mA
ISB1
Automatic CE
Power-Down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
4-ns cycle, 250 MHz
120
mA
5-ns cycle, 200 MHz
110
mA
6-ns cycle, 166 MHz
100
mA
7.5-ns cycle, 133
MHz
90
mA
ISB2
Automatic CE
Power-down
Current—CMOS Inputs
VDD = Max, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ –
0.3V, f = 0
All speeds
40
mA
Shaded areas contain advance information.
Notes:
9. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2).
10. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200ms. During this time VIH < VDD and VDDQ < VDD.
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