IS62WV12816ALL,

IS62WV12816BLL

7

Rev. E

06/08/05

45 ns

55 ns

70 ns

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Read Cycle Time

45

—

55

—

70

—

ns

Address Access Time

—

45

—

55

—

70

ns

Output Hold Time

10

—

10

—

10

—

ns

CS1/CS2 Access Time

—

45

—

55

—

70

ns

OE Access Time

—

20

—

25

—

35

ns

OE to High-Z Output

—

15

—

20

—

25

ns

OE to Low-Z Output

5

—

5

—

5

—

ns

CS1/CS2 to High-Z Output

0

15

0

20

0

25

ns

CS1/CS2 to Low-Z Output

10

—

10

—

10

—

ns

LB, UB Access Time

—

45

—

55

—

70

ns

LB, UB to High-Z Output

0

15

0

20

0

25

ns

LB, UB to Low-Z Output

0

—

0

—

0

—

ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4 to 1.4V and

output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.