ADT7466

Rev. 0 | Page 4 of 48

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DRIVE OUTPUTS (DRIVE1, DRIVE2)

Output Voltage Range

0–2.2

V

Digital input = 0x00 to 0xFF

Output Source Current

2

mA

Output Sink Current

0.5

mA

DAC Resolution

8

Bits

Monotonicity

8

Bits

Differential Nonlinearity

±1

LSB

Integral Nonlinearity

±1

LSB

Total Unadjusted Error

±5

%

REFERENCE VOLTAGE OUTPUT

(REFOUT)

Output Voltage

2.226

2.25

2.288

V

Output Source Current

10

mA

Output Sink Current

0.6

mA

OPEN-DRAIN SERIAL DATA BUS

OUTPUT (SDA)

0.4

V

0.1

1

µA

DIGITAL INPUTS (SCL, SDA, TACH

INPUTS, PROCHOT)

2.0

V

0.8

V

Hysteresis

0.5

V

DIGITAL INPUT CURRENT (TACH

INPUTS, PROCHOT)

−1

µA

1

µA

20

pF

OPEN-DRAIN DIGITAL OUTPUTS

(ALERT, FANLOCK, FAN1_ON/THERM)

0.4

V

0.1

1

µA

SERIAL BUS TIMING 2

400

kHz

See Figure 2

50

ns

See Figure 2

1.3

µs

See Figure 2

0.6

µs

See Figure 2

0.6

µs

See Figure 2

1.3

µs

See Figure 2

0.6

µs

See Figure 2

1000

ns

See Figure 2

300

ns

See Figure 2

100

ns

See Figure 2

25

64

Ms

Can be optionally disabled

accept input high voltages up to 5 V even when the device is operating at supply voltages below 5 V. Timing specifications are tested at logic levels of V = 0.8 V for a

falling edge and at V = 2.0 V for a rising edge.

A

IL

IH