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ADT7466ARQZ-REEL7 Datasheet(PDF) 4 Page - Analog Devices |
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ADT7466ARQZ-REEL7 Datasheet(HTML) 4 Page - Analog Devices |
4 / 48 page ADT7466 Rev. 0 | Page 4 of 48 Parameter Min Typ Max Unit Test Conditions/Comments DRIVE OUTPUTS (DRIVE1, DRIVE2) Output Voltage Range 0–2.2 V Digital input = 0x00 to 0xFF Output Source Current 2 mA Output Sink Current 0.5 mA DAC Resolution 8 Bits Monotonicity 8 Bits Differential Nonlinearity ±1 LSB Integral Nonlinearity ±1 LSB Total Unadjusted Error ±5 % IL = 2 mA REFERENCE VOLTAGE OUTPUT (REFOUT) Output Voltage 2.226 2.25 2.288 V Output Source Current 10 mA Output Sink Current 0.6 mA OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA) Output Low Voltage (VOL) 0.4 V IOUT = −4.0 mA, VCC = 3.3 V High Level Output Current (IOH) 0.1 1 µA VOUT = VCC DIGITAL INPUTS (SCL, SDA, TACH INPUTS, PROCHOT) Input High Voltage (VIH) 2.0 V Input Low Voltage (VIL) 0.8 V Hysteresis 0.5 V DIGITAL INPUT CURRENT (TACH INPUTS, PROCHOT) Input High Current (IIH) −1 µA VIN = VCC Input Low Current (IIL) 1 µA VIN = 0 Input Capacitance (IN) 20 pF OPEN-DRAIN DIGITAL OUTPUTS (ALERT, FANLOCK, FAN1_ON/THERM) Output Low Voltage (VOL) 0.4 V IOUT = −4.0 mA, VCC = 3.3 V High Level Output Current (IOH) 0.1 1 µA VOUT =VCC SERIAL BUS TIMING 2 Clock Frequency (fSCLK) 400 kHz See Figure 2 Glitch Immunity (tSW) 50 ns See Figure 2 Bus Free Time (tBUF) 1.3 µs See Figure 2 Start Setup Time (tSU;STA) 0.6 µs See Figure 2 Start Hold Time (tHD;STA) 0.6 µs See Figure 2 SCL Low Time (tLOW) 1.3 µs See Figure 2 SCL High Time (tHIGH) 0.6 µs See Figure 2 SCL, SDA Rise Time (tr) 1000 ns See Figure 2 SCL, SDA Fall Time (tf ) 300 ns See Figure 2 Data Setup Time (tSU;DAT) 100 ns See Figure 2 Detect Clock Low Timeout (tTIMEOUT) 25 64 Ms Can be optionally disabled 1 All voltages are measured with respect to GND, unless otherwise specified. Typical values are at T = 25°C and represent the most likely parametric norm. Logic inputs accept input high voltages up to 5 V even when the device is operating at supply voltages below 5 V. Timing specifications are tested at logic levels of V = 0.8 V for a falling edge and at V = 2.0 V for a rising edge. A IL IH 2 Guaranteed by design, not production tested. |
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